[SI-LIST] Spice Noise Analysis

Hi,

May be this question is slightly out of topic in this list,but since
there are people with wide experiences i would like get your opinion.

My query is,

Has anybody done Spice Noise Simulations(say in Hspice) on chip level
macros or components, with the inherent noise contributed from
individual components(like MOS transistors etc) included.?

If so can you enlighten me more about it.There is some info mentioned
in Hspice manual,but if anybody in this group has more insight please
assist me.

This is on top of Power rail noise.(for timing Jitter calculations)

Thanks in advance..

Pramod
Circuit Design
LSI Logic India
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