Posts for si-list, 07-2006

Browse: Last Month: 06-2006 Main Archive Page Next Month: 08-2006

» [SI-LIST] Re: Using W-element in Spectre -
» [SI-LIST] Re: How to use RLC matrix files -
» [SI-LIST] How to use RLC matrix files -
» [SI-LIST] Michael W Wielebski/Mequon/RA/Rockwell is out of the office. -
» [SI-LIST] tool update -
» [SI-LIST] Re: Single tip probe accuracy -
» [SI-LIST] Single tip probe accuracy -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Job opening: Signal Integrity Engineer -
» [SI-LIST] High Speed webinar, Aug 2 -
» [SI-LIST] Re: Hidden noise margin problems -
» [SI-LIST] Re: Hidden noise margin problems -
» [SI-LIST] Re: IBIS modeling Seminar in Fremont Aug 14-15 -
» [SI-LIST] Re: Hspice temperature as a variable -
» [SI-LIST] Re: High speed USB Query -
» [SI-LIST] IBIS modeling Seminar in Fremont Aug 14-15 -
» [SI-LIST] Re: Antwort: Re: 90 degree turn in PCB tracks (repeat) -
» [SI-LIST] Re: Antwort: Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Hidden noise margin problems -
» [SI-LIST] High speed USB Query -
» [SI-LIST] Re: Hspice temperature as a variable -
» [SI-LIST] Re: Hspice temperature as a variable -
» [SI-LIST] Job posting - Altera technical marketing for signal integrity -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Hspice temperature as a variable -
» [SI-LIST] Re: Hspice temperature as a variable -
» [SI-LIST] Hspice temperature as a variable -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: Antwort: Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: Antwort: Re: 90 degree turn in PCB tracks -
» [SI-LIST] FW: Electrical Requirements for Packaging class -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Antwort: Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Antwort: Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: EMI analysis tools? -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: EMI analysis tools? -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Antwort: Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: 90 degree turn in PCB tracks -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] 90 degree turn in PCB tracks -
» [SI-LIST] Re: high frequency current measurements -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] EMI analysis tools? -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: high frequency current measurements -
» [SI-LIST] Re: high frequency current measurements -
» [SI-LIST] high frequency current measurements -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Re: Current Return Vias -
» [SI-LIST] Current Return Vias -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] same odd and even impedance implications -
» [SI-LIST] Video System Engineer needed in Santa Clara, CA; -
» [SI-LIST] Re: Vacation Messages -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Dell SI job openings -
» [SI-LIST] Re: Vacation Messages -
» [SI-LIST] Re: Vacation Messages -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Need your Opinion and expertise -
» [SI-LIST] Re: HSPICE model to IBIS model conversion for SI analysis -
» [SI-LIST] Re: HSPICE model to IBIS model conversion for SI analysis -
» [SI-LIST] Re: HSPICE model to IBIS model conversion for SI analysis -
» [SI-LIST] HSPICE model to IBIS model conversion for SI analysis -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: Need your Opinion and expertise -
» [SI-LIST] Re: Need your Opinion and expertise -
» [SI-LIST] Re: Need your Opinion and expertise -
» [SI-LIST] Re: Need your Opinion and expertise -
» [SI-LIST] Re: Using W-element in Spectre -
» [SI-LIST] Using W-element in Spectre -
» [SI-LIST] Re: HSPICE variable name length limit? -
» [SI-LIST] Re: Vacation Messages -
» [SI-LIST] Re: Vacation Messages -
» [SI-LIST] Re: Vacation Messages -
» [SI-LIST] Re: Vacation Messages -
» [SI-LIST] Vacation Messages -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] HSPICE variable name length limit? -
» [SI-LIST] Re: Need your Opinion and expertise -
» [SI-LIST] Re: Need your Opinion and expertise -
» [SI-LIST] Using W-element in Spectre -
» [SI-LIST] Re: DDR-1 Termination -
» [SI-LIST] DDR-1 Termination -
» [SI-LIST] Need your Opinion and expertise -
» [SI-LIST] Re: [SPAM] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: [SPAM] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: ADC layout: moving from PCB to chip -
» [SI-LIST] Re: si-list Digest V6 #258 -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: si-list Digest V6 #258 -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: ADC layout: moving from PCB to chip -
» [SI-LIST] Re: ADC layout: moving from PCB to chip -
» [SI-LIST] IBIS-4.1/AMS tutorial at DesignCon -
» [SI-LIST] Re: ADC layout: moving from PCB to chip -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: ADC layout: moving from PCB to chip -
» [SI-LIST] Fwd: Re: Re: SDRAM Routing Topology - Follow Up -
» [SI-LIST] Re: SDRAM Routing Topology - Follow Up -
» [SI-LIST] Re: SDRAM Routing Topology - Follow Up -
» [SI-LIST] Re: ADC layout: moving from PCB to chip -
» [SI-LIST] Early history of signal measurements and EMC -
» [SI-LIST] Re: SDRAM Routing Topology - Follow Up -
» [SI-LIST] ADC layout: moving from PCB to chip -
» [SI-LIST] Re: SDRAM Routing Topology - Follow Up -
» [SI-LIST] Re: SDRAM Routing Topology - Follow Up -
» [SI-LIST] Re: SDRAM Routing Topology - Follow Up -
» [SI-LIST] Re: SDRAM Routing Topology -
» [SI-LIST] Re: SDRAM Routing Topology -
» [SI-LIST] Hardware characterization/SI/Labview project in Sunnyvale, CA -
» [SI-LIST] HELP -
» [SI-LIST] INFO -
» [SI-LIST] Transmission lines: book commentary - Thanks for the responses. -
» [SI-LIST] Re: Fundamental vs Overtone crystal -
» [SI-LIST] Re: OLL-140 S-Parameters, can be viewed for free in July -
» [SI-LIST] Re: OLL-140 S-Parameters, can be viewed for free in July -
» [SI-LIST] Re: Transmission lines: book commentary -
» [SI-LIST] Re: Fundamental vs Overtone crystal -
» [SI-LIST] Re: Fundamental vs Overtone crystal -
» [SI-LIST] Re: Transmission lines: book commentary -
» [SI-LIST] Re: Transmission lines: book commentary -
» [SI-LIST] Transmission lines: book commentary -
» [SI-LIST] Fundamental vs Overtone crystal -
» [SI-LIST] Re: AC97 Audio layout -
» [SI-LIST] OLL-140 S-Parameters, can be viewed for free in July -
» [SI-LIST] AC97 Audio layout -
» [SI-LIST] Test -
» [SI-LIST] Re: ESD on USB Connector Shield -
» [SI-LIST] Re: ESD on USB Connector Shield -
» [SI-LIST] Re: ESD on USB Connector Shield -
» [SI-LIST] ESD on USB Connector Shield -
» [SI-LIST] Re: Simulation -
» [SI-LIST] Re: Simulation -
» [SI-LIST] Re: Simulation -
» [SI-LIST] Simulation -
» [SI-LIST] Re: Trace Spacing Rule -
» [SI-LIST] Rise time for differential signals -
» [SI-LIST] Re: AC coupling HDMI signals -
» [SI-LIST] A small change can have a large effect - part 2 -
» [SI-LIST] Memory Interface placement and routing Topology. -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] help-Loading analysis -
» [SI-LIST] Re: Question on AC coupling -
» [SI-LIST] Question on AC coupling -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] IBIS Class August 14-15 -
» [SI-LIST] Re: AC coupling HDMI signals -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: AC coupling HDMI signals -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] AC coupling HDMI signals -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] custom ceramic capacitors -
» [SI-LIST] Re: Strange non-monotonic edge after LVPECL and LVDS interface circuit -
» [SI-LIST] IBIS 4.2 Golden Parser Released! -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: SDRAM Routing Topology -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] SDRAM Routing Topology -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Re: Fibre channel interconnect margins -