[SI-LIST] Re: HSTL and SSTL
- From: Bill.Cohen@xxxxxxxxxxxxxxxx
- To: arun@xxxxxxxxxxxxxxxx
- Date: Wed, 20 Sep 2006 11:22:16 -0400
ARUN,
The standard for HSTL is at:
http://www.jedec.org/download/search/jesd8-6.pdf
SSTL can also be found in two documents on the JEDEC Website:
JESD8-15A
Published: Sep-2003
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STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18):
This standard defines the input, output specifications and ac test
conditions for devices that are designed to operate in the SSTL_18 logic
switching range, nominally 0 V to 1.8 V. The standard may be applied to
ICs operating with separate VDD and VDDQ supply voltages. The VDD value
is not specified in this standard; however VDD and VDDQ will have the
same voltage level in many cases.
JESD79-2C
Published: May-2006
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DDR2 SDRAM SPECIFICATION
This comprehensive standard defines all required aspects of 256Mb through
4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout,
addressing, functional description, features, ac and dc parametrics,
truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface,
which is described in another JEDEC standard called JESD8-15. The purpose
of this Standard is to define the minimum set of requirements for
compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System
designs based on the required aspects of this specification will be
supported by all DDR2 SDRAM vendors providing compliant devices. Changes
between versions is indicated in Annex A.
--------------------------------------------------------------
| Bill Cohen
| Toshiba America Electronic Components
| Mixed Signal Design Group
--------------------------------------------------------------
"Arun Kumar"
<arun@e-consystem
s.com> To
Sent by: <si-list@xxxxxxxxxxxxx>
si-list-bounce@fr cc
eelists.org
Subject
[SI-LIST] HSTL and SSTL
09/20/2006 11:37
PM
Please respond to
arun@e-consystems
.com
Hi,
I want to know more details about HSTL and SSTL.
Please guide more about the same.
ARUN
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On
Behalf Of Peterson, James F (EHCOE)
Sent: Wednesday, September 20, 2006 5:16 AM
To: Benny Yan
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: OUTPUT IMPEDANCE CALCULATION [IBIS]
by the way, in the equation I wrote below the "3D" is a formatting
artifact and shouldn't be in the equation...
(I'll try again to write here); Vout <equals> Vin * (Zo/(Zo+Zs)) ...and
solving for Zs
-Jim
________________________________
From: Benny Yan [mailto:bennyzhi@xxxxxxxxx]
Sent: Tuesday, September 19, 2006 8:10 PM
To: Peterson, James F (EHCOE)
Cc: torocar@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: OUTPUT IMPEDANCE CALCULATION [IBIS]
Eric Bogatin mentioned a method in his book<Signal
Integrity:Simplified>.
Benny Yan
On 9/19/06, Peterson, James F (EHCOE) <james.f.peterson@xxxxxxxxxxxxx>
wrote:
Another method to establish the source impedance (Zs) of a
driver from
an IBIS model is in a simulation (still using Ohms law):
Create a circuit with the ibis model driving a very long
transmission
line (12 inches) with a known trace impedance (Zo). Drive the
line both
high and low and observe the porch in the waveform. The porch is
caused
by the ratio of Zs and Zo. Zs can be solved by rearranging this
very
familiar equation :
Vout =3D Vin * (Zo/(Zo+Zs)) ...solve for Zs, Vout is Vporch and
Vin is =
the
total voltage swing
The porch will last as long as 2x the propagation time of the
T-line.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Scott McMorrow
Sent: Monday, September 18, 2006 4:48 PM
To: torocar@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: OUTPUT IMPEDANCE CALCULATION [IBIS]
Carlos
Ohms law (Z=3D V/I). You have a V/I curve at min/typ/max device
=
corners.
regards,
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed(r) is the registered service mark of Teraspeed
Consulting
Group LLC
Carlos Toro wrote:
> Hello members of the SI list.
> Does anyone has experience with calculating the output
impedance of a=20
> microcontroller pin given its IBIS model?.
>
> I don't have access to the silicon yet, just the IBIS for now.
I=20
> intend to match impedances of critical PCB traces of our
design.
>
> Thanks in advance.
>
>
> =20
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=20
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- References:
- [SI-LIST] HSTL and SSTL
- From: Arun Kumar
Other related posts:
- » [SI-LIST] HSTL and SSTL
- » [SI-LIST] Re: HSTL and SSTL
- » [SI-LIST] Re: HSTL and SSTL
- [SI-LIST] HSTL and SSTL
- From: Arun Kumar