Posts for si-list, 03-2011

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  1. » [SI-LIST] Re: EBD model of DDR2 RDIMM R/C G, Lance Wang
  2. » [SI-LIST] 40th anniversary of SPICE: EDN & IEEE articles, colin_warwick
  3. » [SI-LIST] Detecting problems in an ESD simulator, Doug Smith
  4. » [SI-LIST] 回复： Re: EBD model of DDR2 RDIMM R/C G, John Lee
  5. » [SI-LIST] Re: Detecting problems in an ESD simulator, Larry Stillings
  6. » [SI-LIST] HFSS wave port, Jagan Rajagopalan
  7. » [SI-LIST] Advice needed for how to make my PCB thicker, Henrik Gildå
  8. » [SI-LIST] High-Speed Signaling Tutorial at WMED 2011, Tim Hollis (thollis)
  9. » [SI-LIST] Experienced high frequency package design engineer or consultant, bradsg@xxxxxxxxxxxx
  10. » [SI-LIST] DDR3 from different vendor, Gen Huang
  11. » [SI-LIST] Reference planes for ethernet signals, jhasson
  12. » [SI-LIST] SI Hardware Engineer Opening, Josefosky, John
  13. » [SI-LIST] Touchstone 2.0, Havermann, Gert
  14. » [SI-LIST] touchstone 2.0 Link, Havermann, Gert
  15. » [SI-LIST] Signal Integrity Jobs at Cisco Bangalore, Goutham Sabavat (gsabavat)
  16. » [SI-LIST] RE Re: Reference planes for ethernet signals, jhasson
  17. » [SI-LIST] Re: RE Re: Reference planes for ethernet signals, jhasson
  18. » [SI-LIST] [Fwd: Re: RE Re: Reference planes for ethernet signals], steve weir
  19. » [SI-LIST] Senior Electrical Engineer Job Posting in Albuquerque, NM, Samantha Jaramillo
  20. » [SI-LIST] Senior Signal Integrity Job opporunity at Cisco San Jose, Jianming Li (jianmili)
  21. » [SI-LIST] Re: OT: Overvoltage breakdown on 120 nm silicon? - conclusion, Dimiter Popoff
  22. » [SI-LIST] Sr. Signal Integrity Engineer Position at Oracle, Derek Tsai
  23. » [SI-LIST] Re: HSPICE xtalk simulation, Lakshmi Narayanan Sowrirajan, ERS-HCLTech
  24. » [SI-LIST] Job Posting: Characterization Architect, Mark Alexander
  25. » [SI-LIST] Definitions in IPC-T-50, Jack Olson
  26. » [SI-LIST] 3D EM Solver/Simulator, Rachel Sheve
  27. » [SI-LIST] SI Lead @ Apple, Sandy Perlman
  28. » [SI-LIST] R: 3D EM Solver/Simulator, gianguida@xxxxxxxx
  29. » [SI-LIST] R: Re: SI job opening at..., gianguida@xxxxxxxx
  30. » [SI-LIST] Opportunity at Intel India| Signal Integrity, Sharma, PriyankaX G
  31. » [SI-LIST] Measuring common mode return loss, Juan G Fuentes
  32. » [SI-LIST] Re: Measuring common mode return loss, Peter . Pupalaikis
  33. » [SI-LIST] respond, Jimmy Lee
  34. » [SI-LIST] European IBIS Summit at SPI 2011 - First Call for Papers/Participation, Lance Wang
  35. » [SI-LIST] Looking for SI job, ma mu
  36. » [SI-LIST] SoC - DDR2 clock jitter vs filler cell count?, Graham Kus
  37. » [SI-LIST] [Job] Opportunity for EM-Solver Whiz & RFIC CAD Specialist (Los Angeles, CA), Rachel Sheve
  38. » [SI-LIST] Re: corrected Excel files and DesignCon 2011 papers posted at electrical-integrity.com, Istvan Novak
  39. » [SI-LIST] set si-list digest2, Graham Kus
  40. » [SI-LIST] IBISCHK5 version 5.0.6 now available!, Mirmak, Michael
  41. » [SI-LIST] Resonance on the pcb board, John Smith
  42. » [SI-LIST] S parameters, Nijagunamurthy, Hithesh (GE Intelligent Platforms)
  43. » [SI-LIST] HSPICE deck for single ended TDR, Dan
  44. » [SI-LIST] hunt for a HS-USB(ULPI) IBIS model, myazx
  45. » [SI-LIST] Regarding RF circuit (Communicationof Tx/Rx Problem), Prabhakar Mohan
  46. » [SI-LIST] VIA-FillingMaterial, johny leon
  47. » [SI-LIST] only 7 days to go - 4th FPGA Camp - 6'Apr 2011 Silicon Valley, Vikram Singh
  48. » [SI-LIST] AW: Re: only 7 days to go - 4th FPGA Camp - 6'Apr 2011 Silicon Valley, Havermann, Gert