[SI-LIST] Re: OT: Overvoltage breakdown on 120 nm silicon? - conclusion
- From: Dimiter Popoff <dp@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 15 Mar 2011 2:18:28 +0200
Hi and thanks to everyone who followed this and commented.
It turned out the CPU had been killed after all (replaced it
yesterday, had to wait for delivery).
I had never seen a chip damaged in such a subtle way (but then again,
I am not involved much in production where these things must be more
common).
Something inside the data cache had died - in a way it failed
only when the CPU would write a 32 bit word with autodecrement
(OK, on PPC this is writing at -4,Rn with update to Rn) and
this would happen on a cache hit. Locking the cache had made
the system boot (and completely useless, way too slow).
This must have been caused by an overvolatege event on the
1.5V core supply. Not sure how high, must have been
between 2.5 and 3V (absolute max. rating being 1.8).
The on-CPU-chip clamping diodes are unlikely to have been driven
open, the 1.5V power is 1N5819 (Shottky) clamped to both the 2.5 and
the 3.3V.
I stoppped posting on that thread when someone suggested it
was quite a pain to witness someones troubleshooting, I had
not realized this could be the case (had just missed the obvious).
So I am posting this now to have at least some finishing line
to that troubleshooting story you all witnessed (I imagine it is
better this way than to leave it open).
Dimiter
------------------------------------------------------
Dimiter Popoff Transgalactic Instruments
http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/
>Date: Thu, 17 Feb 2011 10:52:15 -0800
>From: steve weir <weirsi@xxxxxxxxxx>
>To: Dimiter Popoff <dp@xxxxxxxxxxx>
>CC: si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] OT: Overvoltage breakdown on 120 nm silicon?
>
>Memories have been known to suffer cell damage from OV / UV transients
>at the I/Os. Many engineers think that if damage comes via the I/O that
>the I/O will show up problems first. That's not always true. In the
>1990's I recall static RAM memories from one vendor in particular that
>were far more vulnerable than from other vendors. Your device may have
>been ESD'd, or a victim of too many OV/UV transients at the I/Os. Stuff
>happens.
>Dimiter Popoff wrote:
>> I am facing an unbelievable reality at the moment.
>> A processor which will not boot - although all tests I have
>> done to it pass.
>>
>> I still refuse to believe I can have killed the CPU - but after
>> 3 days of tracing of the boot process I seem to run out of
>> other explanations (heck, I had to dig through code some of
>> which I have written 15+ years ago...).
>>
>> The CPU (an MPC5200B) appears to work - monitor via UART, even disk
>> I/O worked etc. - but it fails some way into the boot process.
>> This happened after I fixed the power up sequencing closer to
>> the specs :-).
>>
>> That board had been working for nearly a year before that, had survived
>> the development process (lots of programming/debugging and power on/off).
>> It had lived through all that with a nice spike on the 1.5V, 2.5V and 3.3V
>> upon poweron, perhaps 1 to 5mS over the absolute maximum by perhaps
>> 50%. I changed that now - and it won't boot, fails at more or less
>> the same place (pulls the wrong return address from the stack if I am
>> not tracing ....). This is after a few system calls have returned OK
>> already. It looks unbelievable to me to have killed the CPU in such
>> a subtle way - but I have not seen many killed ones.
>>
>> How likely is it that I have killed it? The only news about the
>> spikes which I believe to may have killed it is that I now know they
>> used to exist...
>> Not to speak of the other boards which keep on workingfine :).
>>
>> I also made the CPU check almost all of the 64M DDRAM, write address
>> to location/verify - works, did that with the written address rotated
>> 0 to 31 times, also works.... And all that also misaligned,
>> also works fine - it is pretty maddening really.
>>
>> I am simply clueless as to how likely it is to break a gate
>> with say 2.5V instead of 1.5? I guess drain/source breakdown won't
>> be an issue even if they break for a few mS (not enough energy
>> to fry anything)?
>>
>> Hopefully people with more silicon inside knowledge can
>> comment...
>>
>> Thanks,
>> Dimiter
>>
>> ------------------------------------------------------
>> Dimiter Popoff Transgalactic Instruments
>>
>> http://www.tgi-sci.com
>> ------------------------------------------------------
>> http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/
>>
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