[SI-LIST] Re: Sr. Signal Integrity Engineer Position at Oracle
- From: Derek Tsai <dstsai704@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 14 Mar 2011 19:59:55 -0700
Sorry, the link at the end of the email is broken.
Please use the below link to apply:
https://irecruitment.oracle.com/OA_HTML/OA.jsp?OAFunc=IRC_VIS_VAC_DISPLAY&OAMC=R&p_svid=1495655&p_spid=1547977
Derek
On 3/14/2011 5:51 PM, Derek Tsai wrote:
> Looking to hire a sr. signal integrity engineer at Oracle.
> Reply to me or apply directly with the link at the end of the mail.
>
> Derek
>
> Job Title Hardware Developer 4
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>
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> Location SANTA CLARA
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> Organization Name x86 Systems - Hardware Validation
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> Department Description
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> Oracle's Systems Group line of business develops computer servers,
> storage and networking equipment for enterprise needs. The X86 group
> of the Systems Group develop blade and rack-mount servers using
> standard x86 CPU and chipsets.
> Job Requirements
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> Work is non-routine and very complex, involving the application of
> advanced technical/business skills in area of specialization. Leading
> contributor individually and as a team member, providing direction and
> mentoring to others. BS or MS degree or equivalent experience relevant
> to functional area. 7 years of engineering or related experience.
>
>
>
> Additional Details
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> Signal Integrity Engineer:
> Works with the board designers to arrive at an optimal set of board
> routing and design rules to ensure optimal noise and timing margin for
> manufacturability of the hardware products. Prior to board layout,
> evaluate the various design parameters including I/O timing budget,
> number/type/placement of decoupling capacitors, routing topology -
> using SPICE/SiSoft simulator or based on measurements on test
> vehicles. As part of the validation process, perform post-layout
> verification of the signal and power planes on the board using
> verification tools such as SpecctraQuest or SiSoft. All of the signal
> integrity work strives to meet the aggressive, leading-edge system
> performance and reliability. Must understand the system design
> trade-offs. PLL application experience is a plus.
>
> Required Knowledge and Skills:
> Solid electronic circuit background
> Good electromagnetic (EM) or EMI knowledge
> In depth knowledge of high-speed design, transmission-line theory
> field-sovling methods, noise analysis and EMC techniques
> Expert in building models from transistor level and conversion to
> behavioral models (IBIS or SPICE) for use in full system level simulation
> Experience with SPICE or other 'analog' simulators.
> Experience with measurement equipment such as oscilloscope, impedance
> analyzer, and network analyzer.
> Some experience with the board design tools such as Allegro or
> BoardStation
> Good communication/presentation skill
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>
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> Location Santa Clara, CA, US
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>
> Please apply here:
> https://irecruitment.oracle.com/OA_HTML/OA.jsp?page=/oracle/apps/irc/candidateSelfService/webui/VisVacDispPG&OAHP=IRC_EXT_SITE_VISITOR_APPL&OASF=IRC_VIS_VAC_DISPLAY&akRegionApplicationId=821&transactionid=1927408076&retainAM=N&addBreadCrumb=RP&p_svid=1495655&p_spid=1547977&oapc=6&oas=9R0Yw-JQWupch_tAlAvtSQ..
>
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