[SI-LIST] High-Speed Signaling Tutorial at WMED 2011

From: "Tim Hollis (thollis)" <thollis@xxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Wed, 2 Mar 2011 15:50:27 -0700
All,
I hope it is appropriate to advertise this - if not I apologize, but I
feel strongly that this announcement will be of great interest to many
on this list:

Bryan Casper, who currently leads the High-Speed Signaling Research
Group at Intel's Circuit Research Lab is giving a 2-hour tutorial at the
2011 Workshop on Microelectronics and Electron Devices to be held April
22, 2011 in Boise, Idaho. For those of you familiar with Bryan's work,
you will realize what an opportunity this is, especially when
considering the registration cost is only $50 for IEEE members and $75
otherwise. Bryan has given similar tutorial/forum presentations at ISSCC
in 2006 and ISCAS in 2008, and by comparison, attending either of his
earlier presentations would have cost more than $600 with the full
conference registration. In addition, the WMED is a much more intimate
setting, which will enable him to interact with the audience more
readily.
Registration for the 2011 WMED is open and can be found at:
http://wmed2011.eventbrite.com 
Information on the full Workshop program can be found at the official
2011 WMED website:
http://www.ewh.ieee.org/r6/boise/wmed2011/WMED2011.html

Bryan's Presentation is titled: Energy Efficient Multi-Gb/s I/O: Circuit
and System Design Techniques

Abstract:

Chip-to-chip I/O data rates continue to scale aggressively to keep up
with demands brought on by multi-core CPU-based computer and networking
systems. Due to increasing bandwidth needs and declining system power
budgets, dramatically improving I/O energy efficiency is crucial and is
the major challenge currently facing the computer and networking
industry. A multi-pronged approach to I/O power reduction will be
presented, employing both circuit and interconnect optimization. The use
of system level modeling and optimization to co-design the packaging,
board interconnect, channel, transmitter, receiver, and clocking will be
advocated with examples that demonstrate minimum-power I/O systems. I/O
energy reduction depends on both active power minimization as well as
the use of aggressive power management methods. Techniques and
corresponding examples will be shown that demonstrate I/O power
management including dynamic voltage and frequency scaling, low-power
standby, and fast wake-up times. This session will provide insight into
the challenges and opportunities associated with each low-power
technique, using case studies to illustrate state-of-the-art low-power
I/O systems.

Bio:

Bryan Casper is a Principal Engineer with Intel's Circuit Research Lab,
based in Hillsboro, Oregon. He leads Intel's high-speed signaling
research group responsible for the development and design of next
generation high-speed mixed signal circuits and I/O systems. In 1998, he
joined the Performance Microprocessor Division of Intel Corporation and
contributed to the development of the Intel Pentium(r) and Xeon(r)
processors. Since 2000, he has been a circuit researcher, contributing
to the development of I/O self-test technology, signaling analysis
methods, high-speed I/O circuit architectures and multiple I/O
standards.


Thank you,
Tim Hollis
Micron Technology, Inc.
2011 WMED Publicity Chair



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[SI-LIST] High-Speed Signaling Tutorial at WMED 2011

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