[SI-LIST] Senior Signal Integrity Job opporunity at Cisco San Jose
- From: "Jianming Li (jianmili)" <jianmili@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 14 Mar 2011 13:20:38 -0700
SAVBU is looking for a Senior Signal Integrity Engineer in San Jose,
California
If interested, you may submit your resume to me or apply in Cisco
Website when it is active.
External Job Description (r) : Job Title: Senior Signal Integrity
Engineer
Location: San Jose, CA
Opportunity Snapshot
In this role, you will have the opportunity to work in the hardware
engineering team of SAVBU - Cisco's latest acquisition in the Data
Center space. We are looking for candidates who strive in a fast paced
start-up like environment. You will be part of a dedicated team, open
communications, empowerment, innovation, teamwork and customer success
are the foundations of the team. Thus, you set your own limits for
learning and achievements.
We are looking for a motivated Signal Integrity Engineer to contribute
to the development of our next generation product.
http://www.cisco.com/en/US/products/ps10265/index.html
Job Requirements:
- Five plus years of experience in signal integrity
- Hands on person who can do both simulations and lab measurements to
validate the simulation results
- Familiar with multi gigabit serial busses, including PCIe, XAUI, KR,
XFI, and SFI
- Contribute to the signaling and interconnect technology selection
- Definition and simulation of high speed interconnects using simulation
tools
- Familiar with simulation tools such as ADS, Hspice, SpectraQuest, and
CST
- Assess timing, noise margin, crosstalk, signal loss and signal
integrity of all clocks and critical data signaling and develop noise
and timing budgets.
- Has done validation of simulations results using TDR, Network
Analyzer, Oscilloscopes and other lab equipments
- Familiar with package and board co-design methodology
- Has done Package and system level power integrity design methodology
- Backplane design experience and analog circuit knowledge are preferred
- Familiarity with high speed I/Os such as HSTL, SSTL, LVDS, LVPECL, and
serial busses
- Familiar with Memory technologies such as DDR is preferred
- Ability of working effectively with other disciplines a must
- Excellent documentation, communication skills,
- Effective interaction with other engineering discipline skills a must
- Minimum of 5+ years of relative experience with MSEE, PHD preferred.
Manager Specific Requirements :
1) familiar with X86, and PowerPC multi-core processor system design and
PCB layout.
2) 10G SFI and XFI system design and PCB layout.
3) PCIe Gen1/Gen2 and Gen3 protocol and physical layer.
4) Knowledge in 10GBaseT a plus
5) DDR3 memory system design and PCB layout.
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