[SI-LIST] Re: 回复： DDR3 from different vendor

  • From: icer world <icermail@xxxxxxxxx>
  • To: Graham Kus <nemisonic@xxxxxxxxx>, si-list@xxxxxxxxxxxxx, Gen Huang <ghuang1972@xxxxxxxxx>
  • Date: Tue, 22 Mar 2011 01:47:59 -0700 (PDT)

Hi Gen:
    I have serveral suggestions:
1. To do some simulations to compare samsung's dram with the other drams 
in both 
read & write mode;
2. To slow down the work frequency. If the other drams are ok, it's timing 
issue;
3. To change the configurations for the DDR3 interface registers to have try;
Thanks
Icer

________________________________
From: Graham Kus <nemisonic@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx; Gen Huang <ghuang1972@xxxxxxxxx>
Sent: Tue, March 22, 2011 9:11:46 AM
Subject: [SI-LIST] Re: å??å¤?ï¼? DDR3 from different vendor

Hi Gen,
There are a few things that can be going on that depend on the memory size
and organisation of your system.

Some vendors' DRAM variants do not meet standard JEDEC timings in x16
devices. For example Hynix sells a DDR2 device available in x4, x8, and x16,
which has latency settings "6-6-6" with fine-print that "except x16 devices,
which require 6-6-7."

Every vendor has different solutions to the DRAM DLL structure. So your
system must calibrate when it boots, as opposed to using static settings.

For DDR3, some PHY IP vendors only support read and
write leveling calibration on DQ0; so your board must actually connect SoC
DQ0 to DRAM DQ0, and SoC DQ8 to DRAM DQ8, and so on. If you are at an SoC
company, find out which IP vendor you are using and locate this in their
DDR3 PHY documentation.

Furthermore, it is always a good idea to run through some of the application
notes provided by Tier-1 vendors like Micron, Samsung, etc. For example, the
Vref_CA pin must be bypassed to DRAM_VDD, not to DRAM_VSS, and so on. Also
JESD79-3 says to make sure that "spread-spectrum modulation must meet jitter
timing requirements of the DRAM vendor." For example Micron recommends that
for DDR3 spread spectrum clocking, JESD79-2 metrics will work.

We have good experience using the Tektronix DDRA application to validate
DRAM clock constraints across PVT and for different SoC clock
configurations. (Disclosure: I do not work for any DRAM vendor or a Test
equipment vendor, but am experienced with DDR, DDR2, and DDR3 implementation
in embedded systems).

Hope this helps
-Graham

On Sun, Mar 6, 2011 at 11:17 PM, John Lee <venussoso@xxxxxxxx> wrote:

> Hi, Gen,
> There are so many things come to my mind, you need to check: CL/tRCD/tRP
> etc. settings, CMD/ADD setup/hold time, DQ/DQS noise, DQ setup/hold time,
> DQS setup/hold them, RS/TS-DQS settings,  tboard, power noise, board
> stack-up, DRAM datasheet...
> Best Regards!
> John Lee
>
> --- 11å¹´3æ??4æ?¥ï¼?å?¨äº?, Gen Huang <ghuang1972@xxxxxxxxx> å??é??ï¼?
>
>
> å??件人: Gen Huang <ghuang1972@xxxxxxxxx>
> 主�: [SI-LIST] DDR3 from different vendor
> �件人: si-list@xxxxxxxxxxxxx
> æ?¥æ??: 2011å¹´3æ??4æ?¥,å?¨äº?,ä¸?å??4:17
>
>
> I am debugging a DDR3 issue on our boards. We put DDR3-1600 parts from
> Samsung, Elpida and Nanya parts on these boards, of course, each board is
> installed with the drams from the same vendor. For some reason, only those
> boards installed with Samsung parts work stable. Those board installed with
> dram from the other two vendors has  trouble running at 1600Mbps. These
> parts should all be qualified for running DDR3-1600. Does anyone has any
> idea what to look at first?
> Gen
>
>
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