Posts for si-list, 12-2007

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  1. » [SI-LIST] Re: time domain simulation of s-parameter, Saoer Sinaga
  2. » [SI-LIST] Re: Signal crossing Split plane, Jean-Pierre Maurice
  3. » [SI-LIST] Overshoot/undershoot for IO buffer, Shawn Zheng
  4. » [SI-LIST] Xtalk from vertical via to horizontal trace, Shawn Zheng
  5. » [SI-LIST] Re: fiber-weave effect alive and well?, Loyer, Jeff
  6. » [SI-LIST] How many bond-wires to make a good PDS?, Graham Kus
  7. » [SI-LIST] FW: New and lastest reference on "Jitter, Noise, and Signal Integrity at High-Speed", Goodwin, Bernard
  8. » [SI-LIST] Definition of "crosstalk loss" ??, agathon
  9. » [SI-LIST] a technique for injecting noise for troubleshooting, Doug Smith
  10. » [SI-LIST] Passivity/Causality, Ria R
  11. » [SI-LIST] S-par and Spice, Saoer Sinaga
  12. » [SI-LIST] Fw: si-list Digest V7 #410, Gregory R Edlund
  13. » [SI-LIST] : IBIS Vs SPICE matching issue, Sudhanshu SINGH
  14. » [SI-LIST] flat cable model, mohaghtalab
  15. » [SI-LIST] Draft Touchstone 2.0 document available, Mirmak, Michael
  16. » [SI-LIST] Re: Draft Touchstone 2.0 document available, Mirmak, Michael
  17. » [SI-LIST] Free: Spice post-processing environment, nelson.seiden
  18. » [SI-LIST] Diode Termination, Ria R
  19. » [SI-LIST] time-constant=2.3*Z0*CL, Pras venki
  20. » [SI-LIST] VRM, Mohamad Haghtalab
  21. » [SI-LIST] Re: VRM, Alexandre . AMEDEO
  22. » [SI-LIST] PCB trade off, Joel Amzallag
  23. » [SI-LIST] internal time step too small error in transient analysis, boli sudha
  24. » [SI-LIST] ESD on center pin of 6VDC jack input., Chandan M
  25. » [SI-LIST] Re: internal time step too small error in transient analysis, Jory McKinley
  26. » [SI-LIST] Doubt in SSTL_18 dc specPRA, Canes Venatici
  27. » [SI-LIST] ebd simulation in xtk, Leo Hu (jihu2)
  28. » [SI-LIST] Need PCI Express HSPICE model, Joel Brown
  29. » [SI-LIST] About jitter simulation, herry_06
  30. » [SI-LIST] Pk-Pk jitter, Hal Murray
  31. » [SI-LIST] Re: Pk-Pk jitter, olaney
  32. » [SI-LIST] Touchstone Version 2.0 Proposal for S12/S21 Ordering, Bob Ross
  33. » [SI-LIST] op07 IBIS Model, Mohamad Haghtalab
  34. » [SI-LIST] Re: si-list Digest V7 #422, Dmitriev-Zdorov, Vladimir
  35. » [SI-LIST] Chris Heard is out of the office., Chris Heard
  36. » [SI-LIST] Books on PLL design and measurements, art_porter
  37. » [SI-LIST] Re: S parameter to time domain signal, Dmitriev-Zdorov, Vladimir
  38. » [SI-LIST] RLGC Matrix, Mohamad Haghtalab
  39. » [SI-LIST] Re: CML versus ECL/PECL, Srivats Partha
  40. » [SI-LIST] test, Christina Gampala
  41. » [SI-LIST] welcome to our website:www.shijishuma.com, david horan