Posts for si-list, 10-2008

Browse: Last Month: 09-2008 Main Archive Page Next Month: 11-2008

» [SI-LIST] Re: Signal Integrity Tips blog - Puzzle Event 1 - Open the Eye -
» [SI-LIST] Signal Integrity Tips blog - Puzzle Event 1 - Open the Eye -
» [SI-LIST] RF/Microwave Modeling Positions (Nonlinear & Electromagnetics) -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] Re: Best Waveform resolution -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] AW: Re: SMA cable for TDR -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] Best Waveform resolution -
» [SI-LIST] pin pairs -
» [SI-LIST] How to generate an IBIS model for ODT enabled input buffer -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] FW: Re: SMA cable for TDR -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] Re: SMA cable for TDR -
» [SI-LIST] SMA cable for TDR -
» [SI-LIST] Re: multi-drop bidirectional bus -- questions about simulation results -
» [SI-LIST] multi-drop bidirectional bus -- questions about simulation results -
» [SI-LIST] Re: Differential impedance -
» [SI-LIST] Differential impedance -
» [SI-LIST] On-demand recording of free Agilent webcast "Back to Basics: Measurement-Based Channel Modeling for Signal Integrity using Agilent ADS" -
» [SI-LIST] Re: Load calculation and Buffer. -
» [SI-LIST] Re: Load calculation and Buffer. -
» [SI-LIST] Load calculation and Buffer. -
» [SI-LIST] Re: serdes -
» [SI-LIST] Re: serdes -
» [SI-LIST] Re: serdes -
» [SI-LIST] Re: serdes -
» [SI-LIST] Re: serdes -
» [SI-LIST] serdes -
» [SI-LIST] Package design engineer opening at Inphi -
» [SI-LIST] DDR2 memory Down Design -
» [SI-LIST] R: Re: Serpentine patterns for length matching -
» [SI-LIST] Re: Serpentine patterns for length matching -
» [SI-LIST] Re: Serpentine patterns for length matching -
» [SI-LIST] Re: Miniature 50 Ohm delay lines for system integration? -
» [SI-LIST] Re: Serpentine patterns for length matching -
» [SI-LIST] Re: Serpentine patterns for length matching -
» [SI-LIST] October Issue of XrossTalk Magazine Available -
» [SI-LIST] Re: Serpentine patterns for length matching -
» [SI-LIST] Re: Serpentine patterns for length matching -
» [SI-LIST] Re: Serpentine patterns for length matching -
» [SI-LIST] Serpentine patterns for length matching -
» [SI-LIST] Asian IBIS Summit (China) - Sixth Announcement -
» [SI-LIST] links to IEEE EMC Symposium Video and others -
» [SI-LIST] Re: IBIS model doubt -
» [SI-LIST] Re: Diff Z for asymmetric coupled striplines -
» [SI-LIST] Resume -
» [SI-LIST] Re: Miniature 50 Ohm delay lines for system integration? -
» [SI-LIST] Re: Miniature 50 Ohm delay lines for system integration? -
» [SI-LIST] Re: Miniature 50 Ohm delay lines for system integration? -
» [SI-LIST] Miniature 50 Ohm delay lines for system integration? -
» [SI-LIST] Re: Diff Z for asymmetric coupled striplines -
» [SI-LIST] Re: Diff Z for asymmetric coupled striplines -
» [SI-LIST] Re: Diff Z for asymmetric coupled striplines -
» [SI-LIST] Re: Diff Z for asymmetric coupled striplines -
» [SI-LIST] Designlink_xtalk-analysis_Allegro-PCB-SI -
» [SI-LIST] switching power supply magnetic field emissions and SI problems -
» [SI-LIST] Re: Diff Z for asymmetric coupled striplines -
» [SI-LIST] Re: Diff Z for asymmetric coupled striplines -
» [SI-LIST] Re: Diff Z for asymmetric coupled striplines -
» [SI-LIST] Re: Diff Z for asymmetric coupled striplines -
» [SI-LIST] Re: Diff Z for asymmetric coupled striplines -
» [SI-LIST] Diff Z for asymmetric coupled striplines -
» [SI-LIST] Re: upcoming tenth anniversary of website -
» [SI-LIST] Re: Utility Tool for converting Allegro Board Design to IBIS EBD -
» [SI-LIST] Re: stitching capacitors for signals changing reference plane -
» [SI-LIST] Re: stitching capacitors for signals changing reference plane -
» [SI-LIST] Re: stitching capacitors for signals changing reference plane -
» [SI-LIST] Re: stitching capacitors for signals changing reference plane -
» [SI-LIST] Re: IBIS model doubt -
» [SI-LIST] IBIS model doubt -
» [SI-LIST] Re: stitching capacitors for signals changing reference plane -
» [SI-LIST] stitching capacitors for signals changing reference plane -
» [SI-LIST] hi -
» [SI-LIST] Solar Electrical Systems Design Engineer -
» [SI-LIST] Re: TATA-NEN Hottest startup Contest - Perspecte Solutions -
» [SI-LIST] TATA-NEN Hottest startup Contest - Perspecte Solutions -
» [SI-LIST] FW: Signal Integrity Engineer position -
» [SI-LIST] Re: SDA bandwidth -
» [SI-LIST] Signal Integrity Engineer position -
» [SI-LIST] Re: NETWORK MODELS ADJUSTED TO MEASURED TDR DATA. -
» [SI-LIST] obtaning diff param in HSPICE -
» [SI-LIST] NETWORK MODELS ADJUSTED TO MEASURED TDR DATA. -
» [SI-LIST] Anomaly in Jedec DDR2 Derating Tables - part 2 -
» [SI-LIST] Anomaly in Jedec DDR2 Derating Tables -
» [SI-LIST] Re: SDA bandwidth -
» [SI-LIST] Re: SDA bandwidth -
» [SI-LIST] SDA bandwidth -
» [SI-LIST] Re: VNA Measurement Question -
» [SI-LIST] Re: VNA Measurement Question -
» [SI-LIST] Re: VNA Measurement Question -
» [SI-LIST] VNA Measurement Question -
» [SI-LIST] Asian IBIS Summit (Japan) Fourth Announcement -
» [SI-LIST] Re: ARINC 429 and 1553 IBIS models -
» [SI-LIST] Re: ARINC 429 and 1553 IBIS models -
» [SI-LIST] Re: ARINC 429 and 1553 IBIS models -
» [SI-LIST] Re: ARINC 429 and 1553 IBIS models -
» [SI-LIST] Re: ARINC 429 and 1553 IBIS models -
» [SI-LIST] ARINC 429 and 1553 IBIS models -
» [SI-LIST] Re: Adjacent misaligned power planes on a PCB Stackup -
» [SI-LIST] Re: New numerical method for EM problems. -
» [SI-LIST] Re: New numerical method for EM problems. -
» [SI-LIST] Re: New numerical method for EM problems. -
» [SI-LIST] Re: New numerical method for EM problems. -
» [SI-LIST] AW: Re: New numerical method for EM problems. -
» [SI-LIST] Re: New numerical method for EM problems. -
» [SI-LIST] Re: New numerical method for EM problems. -
» [SI-LIST] Re: New numerical method for EM problems. -
» [SI-LIST] Re: New numerical method for EM problems. -
» [SI-LIST] New numerical method for EM problems. -
» [SI-LIST] Re: Adjacent misaligned power planes on a PCB Stackup -
» [SI-LIST] Re: Heat issue in PCB's -
» [SI-LIST] Re: Heat issue in PCB's -
» [SI-LIST] Heat issue in PCB's -
» [SI-LIST] Adjacent misaligned power planes on a PCB Stackup -
» [SI-LIST] EPEP Conference in San Jose this year -
» [SI-LIST] Re: Free Agilent webcast "Back to Basics: Measurement-Based Channel Modeling for Signal Integrity using Agilent ADS" Oct 23 -
» [SI-LIST] Free Agilent webcast "Back to Basics: Measurement-Based Channel Modeling for Signal Integrity using Agilent ADS" Oct 23 -
» [SI-LIST] Re: PCB guides for Ethernet Phy to Connector -
» [SI-LIST] PCB guides for Ethernet Phy to Connector -
» [SI-LIST] Asian IBIS Summit (China) - Fifth Announcement -
» [SI-LIST] Re: IBIS model for external connections -
» [SI-LIST] Re: IBIS model for external connections -
» [SI-LIST] Re: IBIS model for external connections -
» [SI-LIST] Re: IBIS model for external connections -
» [SI-LIST] IBIS model for external connections -
» [SI-LIST] A method of avoiding ESD problems -
» [SI-LIST] Re: IBIS simulation LVPECL -
» [SI-LIST] Re: IBIS simulation LVPECL -
» [SI-LIST] Re: IBIS simulation LVPECL -
» [SI-LIST] Re: IBIS simulation LVPECL -
» [SI-LIST] Re: IBIS simulation LVPECL -
» [SI-LIST] Re: IBIS simulation LVPECL -
» [SI-LIST] Re: IBIS simulation LVPECL -
» [SI-LIST] Re: IBIS simulation LVPECL -
» [SI-LIST] Re: IBIS simulation LVPECL -
» [SI-LIST] IBIS simulation LVPECL -