[SI-LIST] Re: Load calculation and Buffer.

8 mA is a spec limit for the case of a static load, and nothing actually
enforced by the circuit.  The output can source more than that because it
has margin built in.  You don't want to pull more than the spec limit on
a static basis, but dynamic transients are too short to matter so long as
the momentary current demand is not grossly over the limit.  Flip your
calculation around: use your risetime and the spec'd input capacitance to
calculate the transient current, rather than using risetime and assumed
current to calculate capacitance.

Orin Laney
 
On Sun, 26 Oct 2008 10:28:49 +0530 "Nirmale G" <nirmale@xxxxxxxxxxxxxxx>
writes:
> Hi ,
>  
> 
> I have 20 i/o lines from a test board to be interfaced to  FPGA for
> analysis. The test board chip pad can max drive a current of 8mA , 
> max
> frequency is 216MHz , and logic level is 3.3V.
> 
>  
> 
> Calculation for load, C  = I * dt/ dv
> 
>  
> 
> C = 8e-3 * rise time / 3.3 
> 
>  
> 
> Taking Rise time  as (0.46ns)10% of period (4.6 ns) gives the  C = 
> 1.12pF ,
> which is very less . 
> 
> But, For any buffer/ line driver  the typical input capacitance is 5 
> to 7pf
> . 
> 
>  
> 
> Any thoughts on the interface and my calculations for load.
> 
>  
> 
>  
> 
> Regards
> 
> Nirmale G
> 
>  
> 
> 
> 
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