[SI-LIST] Re: multi-drop bidirectional bus -- questions about simulation results

Excellent questions...and it sounds like you did your research before
posting these questions.

I'd check the rise and fall times of the different ibis models. Maybe
the one that isn't giving good wave shapes is a lot faster...might also
be a significant difference in source-Z of the driver.

Once you figured out the cause, then verify with the chip vendor that
the ibis model is accurate.

Also, you mention non-monotonic edges. These ugly edges might be
tolerable if they're just on the databus (you said it was the SDRAM
driving and I'm assuming it isn't DDR SDRAM). So if my assumptions are
correct here (and the ibis model is accurate), then can your timing
analysis tolerate the non-monotonic edges...in other words does your
timing analysis allow enough time for the ugliness to settle out.

Good luck.
Jim



-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Dixon, Adam
Sent: Monday, October 27, 2008 5:14 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] multi-drop bidirectional bus -- questions about
simulation results

I would appreciate comments regarding simulation results and termination
theory/options of a multi-drop bidirectional bus.  The si-list archives
have threads from 2002 to 2007 which have been informative (daisy-chain
vs. star vs. rake topology, source series and end terminations).  I am
simulating a three device bus using Hyperlynx LineSim v7.7 with recently
downloaded IBIS models.  Two of the devices yield good waveshapes
(monotonic edges, acceptable slew rates).  The third device (PC133
SDRAM) has grossly different results based on working with three
different suppliers' models.  Two SDRAM models yield non-monotonic edges
at one receiver and a borderline falling edge knee at the other
receiver.  I initially simulated w/a source series termination at the
SDRAM (10 to 47 ohms) and no SS terminations for the other two devices.
I am now looking at end termination options, though I'd prefer SS if the
simulation results & theory ultimately make sense.
Also, I started searching for multi-drop bidirectional termination
materials in a few SI texts (Chapter 6 in Johnson's High-Speed Digital
Design, Chapter 21 in Ritchey's Right the First Time (Vol. 1) and
Chapter 8 in Bogatin's Signal Integrity-Simplified) and one or two
online app. notes.  End termination is most frequently cited with
explanations for relative component placement, output driver strength,
minimizing stub lengths, etc.  I believe I see simulation results
corresponding to Johnson's note about driver current of CMOS/TTL logic
gates and have been looking at relative component placement and the
"terminator" stub effect of Figure 21.5 in Ritchey's text.  

I'm concerned about the gross difference in SDRAM model behaviors and if
I am overlooking or misunderstanding the topology and simulation method.
I've contacted two of the SDRAM suppliers for feedback and would
appreciate further comment if you have time to discuss.  Thanks very
much!

Cheers,
Adam Dixon, hardware engineer
NCR Corporation
2651 Satellite Blvd.
Duluth, GA  30096
* (770) 623-7093
* ad185064@xxxxxxx


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