[SI-LIST] Load calculation and Buffer.

Hi ,
 

I have 20 i/o lines from a test board to be interfaced to  FPGA for
analysis. The test board chip pad can max drive a current of 8mA , max
frequency is 216MHz , and logic level is 3.3V.

 

Calculation for load, C  = I * dt/ dv

 

C = 8e-3 * rise time / 3.3 

 

Taking Rise time  as (0.46ns)10% of period (4.6 ns) gives the  C = 1.12pF ,
which is very less . 

But, For any buffer/ line driver  the typical input capacitance is 5 to 7pf
. 

 

Any thoughts on the interface and my calculations for load.

 

 

Regards

Nirmale G

 



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