[SI-LIST] DDR2 memory Down Design

Hi Folks,
           We are going through  design guide provided by the silicon vendor 
for Memory Down design.The  length matching  recommendations provided by them 
for  the Onboard memory is 
  1.. Clock pairs should be matched in length to other clock pairs within 20 
mils of each other
  2.. Match total length of ADD/CMD/CTRL to Clocks to within 20 mils
Matching recommendations looks  very odd to see something like CLK+30mils. Also 
they are recommending the address and control signal as a Matched Tree routing 
instead of the Drop down memory routing
As you may know, we normally treat CTRL and ADR/CMD separately, with wider 
length matching window on ADR/CMD, than on CTRL. 

Any comments on this appreciated

Regards
Raja


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: