[SI-LIST] Re: stitching capacitors for signals changing reference plane

Joel,

When stitching capacitors are considered between planes either in 
horizontal
plane splits or in layer-to-layer transitions, usually a major aspect is 
ignored
or overlooked.  It is the fact that if properly designed, the power planes,
together with the attached bypass network, represent a much lower
impedance path between power and ground that what is needed to support
signals.  This means that under most of the circumstances properly
designed power distribution takes care of this question by itself. The 
reason
for this: power distribution networks have to be designed to support not
only the signal return currents, but also the active devices' core 
transients,
as well as they should not exhibit large resonances at higher frequencies
anyway to avoid EMC problems.  As a result, the power distribution network's
impedance should be low compared to signal-loop impedances to begin with.

Stitching capacitors have a possible frequency range, where they may be
effective.  We dont want to stitch the planes at the signal transitions with
large bulk capacitors, but probably the power distribution network has
to have bulk capacitors.  Smaller size stitching capacitors are therefore
not meant for very low frequencies.  At high frequencies, the power-ground
plane capacitance (either directly or indirectly, in case of vertically
stacked multiple power planes) represent a low enough inductance so
that it is hard to compete with it by using discrete capacitors. The
stitching capacitors are therefore effective in the MHz frequency range,
which -as Steve pointed out- can be translated to effective risetime
and distance figures.

Regards,

Istvan Novak
SUN Microsystems


Joel Brown wrote:
> Consider the following stackup:
>  
> L1 - Signal
> L2 - GND
> L3 - PWR
> L4 - Signal
>  
> For signals transitioning from L1 to L4 a stitching capacitor may be needed
> to provide a return path.
> If the signal rise time is slow (say greater than 5 ns) can the stitching
> capacitor be located further from the signal via?
> Is there a relationship between rise time and distance from via to cap that
> is effective?
> Is there a case where the stitching capacitors are not needed if the signal
> is rise time is slow enough?
> If so, where does the current return go and why is it not a problem?
>  
> Thanks - Joel
>  
>
>   

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