[SI-LIST] Re: IBIS model doubt

Canes,
 
All of those parameters you mention are informational,
that is, they do not directly influence or describe the
behavior of the model.  They describe at what condition
the data was generated, or at what conditions certain
timing parameters were obtained.
 
Rest assured that a model generated under a specific
set of conditions will work reasonably well under other
conditions, but even if you have concerns about that,
the IBIS specification does have provisions for providing
V-t tables, for example at multiple sets of V_fixture 
and R_fixture conditions.  And if this is still not
enough, you can always make multiple IBIS models and
use the [Model Selector] keyword to allow the user to
switch between them.
 
But you cannot make a (behavioral) model without any load.
How would you obtain Vmeas, for example?  Or how would the
internal algorithm of an IBIS tool determine what the
output current was when the V-t curves were generated if
there was no V_fixture and R_fixture connected to the
output?
 
I hope this helps to clarify your concern.
 
Arpad
============================================================ 

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Canes Venatici
Sent: Friday, October 17, 2008 12:52 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS model doubt

Hi all,
I haveA some doubts regarding the usage of IBIS models.
In the IBIS model,
1. Ramp measurement is done with a default value of 50ohms (R_load)A
connected to vref.
2. Also Rising/Falling waveformsA can beA simulated/measured with
R_/L_/C_fixture/V_fixture.
3. Cref and RrefA  for specifying the way delay was measured by the
manufacturer.

With the above informationA incorporated in the IBIS file, if used for
simulating
will it be correctly representing the I/O?
For e.g. with R_/L_/C_fixture/V_fixture/R_load effects included in the
waveform data, if I make 
some externalA terminations, it is in addition to the R_fixture/R_load
and may not correctly represent the system.

Instead, whyA don't we have only the un-loaded I/O bufferA modeled in
the IBIS so that
the designer who is using IBIS can put appropriate interface and do the
simulations.

Regards,
Canes


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