Posts for si-list, 10-2007

Browse: Last Month: 09-2007 Main Archive Page Next Month: 11-2007

» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: HSpice field-solver syntax for trapezoidal stripline pair -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] HSpice field-solver syntax for trapezoidal stripline pair -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: Question about VGA termination -
» [SI-LIST] Re: Question about VGA termination -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] Re: DDR2 2-slot design preference... -
» [SI-LIST] DDR2 2-slot design preference... -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] laminate-based package -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Question about VGA termination -
» [SI-LIST] Re: Question about VGA termination -
» [SI-LIST] Question about VGA termination -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Interesting service I saw @ PCB East -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Fw: Re: Dielectric constant measuring -
» [SI-LIST] Re: Dielectric constant measuring -
» [SI-LIST] Re: Dielectric constant measuring -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Dielectric constant measuring -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: DDR2 CMD/CTRL vs. CK Skew compensation problems -
» [SI-LIST] DDR2 CMD/CTRL vs. CK Skew compensation problems -
» [SI-LIST] Result using NEC2++ (2) -
» [SI-LIST] IDE measurement -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Thank you for the SI-LIST -
» [SI-LIST] Thank you for the SI-LIST -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Flight time compensation -
» [SI-LIST] Re: Flight time compensation -
» [SI-LIST] Re: Flight time compensation -
» [SI-LIST] Re: Flight time compensation -
» [SI-LIST] Free SerDes modeling toolkit -
» [SI-LIST] Simulate IBIS model with transmission line?! -
» [SI-LIST] Flight time compensation -
» [SI-LIST] Desperately Seeking SI - Tech Lead for Cisco Systems, Inc. - San Jose, CA -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Re: Help Explaining Microstrip -
» [SI-LIST] Help Explaining Microstrip -
» [SI-LIST] Re: Gigabit ethernet compliance asymmetry test -
» [SI-LIST] Gigabit ethernet compliance asymmetry test -
» [SI-LIST] Re: SI Conferences and Workshops -
» [SI-LIST] ADS Models from TDR/TDT data -
» [SI-LIST] Re: SI Conferences and Workshops -
» [SI-LIST] Sr. Signal Integrity Engineer Position Available @ Sun Microsystems, Inc. -
» [SI-LIST] Re: Balun measurement -
» [SI-LIST] Re: Balun measurement -
» [SI-LIST] SI Conferences and Workshops -
» [SI-LIST] Re: Balun measurement -
» [SI-LIST] Re: Balun measurement -
» [SI-LIST] Re: A ibis problem in Hyperlynx simulation -
» [SI-LIST] R: Re: Trace Width and Skin Effect Loss -
» [SI-LIST] Re: Survey of SI analysis software -
» [SI-LIST] Re: Survey of SI analysis software -
» [SI-LIST] Re: Survey of SI analysis software -
» [SI-LIST] Re: Survey of SI analysis software -
» [SI-LIST] Re: Survey of SI analysis software -
» [SI-LIST] Re: Trace Width and Skin Effect Loss -
» [SI-LIST] Survey of SI analysis software -
» [SI-LIST] Re: A ibis problem in Hyperlynx simulation -
» [SI-LIST] Re: Free Waveform viewer -
» [SI-LIST] Re: Trace Width and Skin Effect Loss -
» [SI-LIST] A ibis problem in Hyperlynx simulation -
» [SI-LIST] Re: Free Waveform viewer -
» [SI-LIST] Re: Trace Width and Skin Effect Loss -
» [SI-LIST] Trace Width and Skin Effect Loss -
» [SI-LIST] Reminder: CIE-SF 2007 Annual Short Course, EPMC-04, Latest Development in High Performance Lead-Frame Packaging and Applications, this coming Saturday afternoon at SJSU Engineering Building Room 339 -
» [SI-LIST] Re: IBIS HELP -
» [SI-LIST] IBIS HELP -
» [SI-LIST] Re: Free Waveform viewer -
» [SI-LIST] Re: Request for example transmission line models and their 2d solver -
» [SI-LIST] Re: Free Waveform viewer -
» [SI-LIST] DRAM capacitance -
» [SI-LIST] Re: Free Waveform viewer -
» [SI-LIST] Re: Free Waveform viewer -
» [SI-LIST] Re: Free Waveform viewer -
» [SI-LIST] Re: prescalar -
» [SI-LIST] prescalar -
» [SI-LIST] Free Waveform viewer -
» [SI-LIST] PCI, FPGA, Orcad BSEE Engineer needed at Mobilygen; -
» [SI-LIST] Package Layout Resource -
» [SI-LIST] Re: AC Coupled Signals -
» [SI-LIST] Re: AC Coupled Signals -
» [SI-LIST] First Pass System Success Workshop -
» [SI-LIST] Re: AC Coupled Signals -
» [SI-LIST] noise injection for troubleshooting -
» [SI-LIST] Re: What to do with "isolation" conductors in ribbon cable? -
» [SI-LIST] DDR memory -
» [SI-LIST] Re: AC Coupled Signals -
» [SI-LIST] Re: AC Coupled Signals -
» [SI-LIST] Re: AC Coupled Signals -
» [SI-LIST] Re: Emission level vary for same type of SATA cables bu t different vendors -
» [SI-LIST] Re: Emission level vary for same type of SATA cables but different vendors -
» [SI-LIST] Re: Emission level vary for same type of SATA cables but different vendors -
» [SI-LIST] Re: Emission level vary for same type of SATA cables but different vendors -
» [SI-LIST] Emission level vary for same type of SATA cables but different vendors -
» [SI-LIST] Re: How to qualify Component Video(YPrPb)?? -
» [SI-LIST] Re: How to qualify Component Video(YPrPb)?? -
» [SI-LIST] Emission level vary for same type of SATA cables but different vendors -
» [SI-LIST] How to qualify Component Video(YPrPb)?? -
» [SI-LIST] Re: What to do with "isolation" conductors in ribbon cable? -
» [SI-LIST] Re: AC Coupled Signals -
» [SI-LIST] Free Webinar about Co-Design b/w IC and Package for Power Integrity -
» [SI-LIST] Re: What to do with "isolation" conductors in ribbon cable? -
» [SI-LIST] Re: si-list Digest V7 #326 -
» [SI-LIST] Re: AC Coupled Signals -
» [SI-LIST] Re: AC Coupled Signals -