[SI-LIST] Re: DDR2 2-slot design preference...
- From: steve weir <weirsi@xxxxxxxxxx>
- To: olaney@xxxxxxxx
- Date: Mon, 29 Oct 2007 13:21:56 -0700
Orin, unless you have a really exotic IC / PCB combination, there is
nothing about an IC's internals that is going to damp a GND-GND PCB
cavity. In order to damp the cavity, the IC would have to attach some
pins to one of the GND planes and others to the second plane and join
those two through a lossy internal connection. I can't recall actually
ever seeing such an arrangement. For the GND-GND case, the GND vias to
the IC will help hold up the via density and therefore the resonant
frequency of the cavity.
In the more difficult case of GND-VCC the biggest modeling problem is
getting the details of the ICs. But once you have them, the tools are
capable of generating very accurate results. Often resonances between
IC internals and the bypass network are a bigger issue than the bypass
network and the PCB.
If there is any doubt as to resonances existing, bias on your devices
and then VNA some portion of the PDN. Now for whatever frequency the
PDN shows parallel resonance between the PCB and the bypass network,
that frequency only moves as the square root of the areal capacitor
density. This leaves us with three basic choices:
a) Move the resonance high enough that we do not excite it.
b) Avoid exciting the cavity, or don't excite it too much.
c) Damp the cavity.
For more fun, do this on a board with sufficiently fast FPGAs and then
load code that intentionally excites the resonance.
Best Regards,
Steve.
olaney@xxxxxxxx wrote:
> Thank you, Lee. I'm skeptical of simulations that ignore the damping
> effect of the nonlinear loads created by populating the board with
> integrated circuits. We've all seen ground planes rattle, but I've
> never seen a problem traceable to cavity resonance between planes. A
> real world example would be welcome.
>
> Orin
>
> On Mon, 29 Oct 2007 10:09:28 -0700 "Lee Ritchey"
> <leeritchey@xxxxxxxxxxxxx> writes:
>
>> I have heard many times about cavity resonances between power and
>> ground
>> planes being the source of problems. However, I have yet to see any
>> clear
>> proof that such things happen and I have never seen a product fail
>> from
>> this in the design of 3000+ PCBs. Could those who claim this
>> happens
>> please supply some evidence of this? Not simulations, but actual
>> measured
>> results and not a statement that the last place it happened was at a
>> client
>> who has an NDA in place that prevents revealing the data.
>>
>> Lee Ritchey
>>
>>
>>
>>> [Original Message]
>>> From: steve weir <weirsi@xxxxxxxxxx>
>>> To: <Monji.Jabori@xxxxxx>
>>> Cc: <si-list@xxxxxxxxxxxxx>
>>> Date: 10/27/2007 2:09:16 PM
>>> Subject: [SI-LIST] Re: DDR2 2-slot design preference...
>>>
>>> Jabori, the issue in each case will be the resonant frequency of
>>>
>> the GND
>>
>>> - GND cavity. Stitch the cavity with an adequate via density to
>>>
>> get the
>>
>>> resonance well above your signal energy and either topology can be
>>>
>> made
>>
>>> to work well.
>>>
>>> Steve.
>>> Jabori, Monji wrote:
>>>
>>>> Hi Experts,
>>>>
>>>>
>>>> I am looking at two designs for a 2-slot DDR2-800 memory system.
>>>>
>> One is
>>
>>>> a butterfly design and the other has the slot on opposite sides
>>>>
>> of the
>>
>>>> motherboard (top and bottom).
>>>>
>>>> I am looking at the GND reference for both designs and have the
>>>> following question knowing that I have to use GND referenced
>>>>
>> layers for
>>
>>>> each DDR2 channel.
>>>>
>>>>
>>>>
>>>> For a butterfly design, my traces on an 8-layer design will flow
>>>>
>> from
>>
>>>> the memory controller via 2 internal layers with 2 different GND
>>>>
>> layers,
>>
>>>> i.e., one slot will have to change GND reference while the other
>>>>
>> will
>>
>>>> not.
>>>>
>>>>
>>>>
>>>> In an opposite 2-slot design, however, we can make the traces
>>>>
>> that go to
>>
>>>> each internal layer have the same GND reference as the DIMM that
>>>>
>> is
>>
>>>> closer to it. For example, the Top DIMM will have the same GND
>>>>
>> reference
>>
>>>> (L2) as its channel traces coming on L3 while the Bottom DIMM
>>>>
>> will have
>>
>>>> its GND reference (L7) as its channel traces coming on L6.
>>>>
>>>>
>>>>
>>>> Having said the above, would you guys prefer one design over
>>>>
>> another
>>
>>>> from an Signal Integrity point of view??
>>>>
>>>>
>>>>
>>>> Thanks in advance.
>>>>
>>>>
>>>>
>>>> Monji
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
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>>>>
>>>>
>>> --
>>> Steve Weir
>>> Teraspeed Consulting Group LLC
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--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
California office
(408) 884-3985 Business
(707) 780-1951 Fax
Main office
(401) 284-1827 Business
(401) 284-1840 Fax
Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax
http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of
Teraspeed Consulting Group LLC
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