[SI-LIST] Re: DDR2 2-slot design preference...
- From: pritchard_jason@xxxxxxx
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 30 Oct 2007 13:32:28 -0400
I contributed to the paper, so I'll try and shed some light on what was
in it...
The purpose of the paper was to explain how high frequency energy can
travel across a PCB and radiate from PCB edges or end up in areas you
didn't expect it to be.=20
If you spend a little time in the lab taking EMI measurements then you
will find out that if you take any board with high speed serial links
with via transitions or stripline routing, and measure around the edge
of the PCB you will almost always find energy there. The question I
always had was, how did it get there? I have been doing SI for many
years so I typically thought about problems in 2 dimensions. The problem
with EMI is it's 3 dimensional. It is sometimes difficult to predict how
energy will travel. The first step is knowing the mechanisms in which
energy gets diverted and spread out across the PCB.=20
The first thing we did was set-up simple experiments in SI-Wave to try
and figure out what was going on. We created simplified etch layouts of
the real board that was having problems. We soon came to the conclusion
that via transitions were exciting resonances on the PCB. What we
determined was that the size of your reference plane and the resultant
cavity resonances created between 2 planes caused energy to travel in
the direction of the resonances when excited by via transitions. This
loss of energy to the planes can also be seen in the s-parameters of the
etch. That is essentially the first half of the paper.=20
We then went into the lab. The experiments were done on a backplane test
board. It only had ground planes. We chose this board because it had SMA
connections and allowed us the flexibility to apply whatever input we
wanted. It also had the same etch/via structures of our problem board,
and proves the point that it doesn't matter if its power or ground. All
you need is 2 metal pieces to create a cavity resonator.=20
The simulations and lab measurements proved that you could predict where
emissions would occur on a PCB. Did this experiment actually solve a
real problem? Indirectly. Once we knew what mechanisms allowed energy to
go to unwanted places on a PCB you can change the layout to accommodate
this. One solution is to use via stitching along the edge of the PCB to
reduce the impedance so that it cant radiate. This was implemented
because the board slipped into metal clips at the edges of the PCB. If
you can squelch the noise before it gets to the metal clips you can
reduce the amount of energy directly coupled to the chassis. Another
solution would be to make sure your return path impedance is very low
along all of your high speed signals which is very difficult in high
density boards.=20
You could consider via fencing along the edge of a PCB a "rule of
thumb", but it's a useful one because I have yet to see anyone capable
of looking at a PCB and tell me how the energy is going to travel across
the PCB, couple, and radiate. This is not a 2D SI problem its 3D.
Obviously you could put the work in and simulate it, but that is often
time consuming and not available to most people.=20
We were going to present the REAL board results at design con in
February but it wasn't in the cards this year.=20
I am not an EMI "guru". I just wanted to understand what is happening.
Just because you haven't seen it doesn't mean it doesn't exist.=20
References:=20
* Reducing Simultaneous switching noise and emi on ground/power planes
by dissipative edge termination. Istvan
* EMI mitigation with multilayer Power Bus Stacks and via stitching of
reference planes. Xiaoning ye, David M. Hockanson, Min Li,.....
* Radiated Emission from a multilayer PCB with traces placed between
power/ground planes. Takashi Harada, Hideki Sasaki, Toshihide Kuriyama
* Reduction in radiated emission by symmetrical power-ground layer
stack-up pcb no open edge. Satoru Haga, Ken Nakano, Osamu Hashimoto
* The Radiation of a rectangular power bus structure at multiple cavity
mode resonances. Marco Leone
* Coupling of through hole signal via to power/ground references and
excitation of edge radiation in multilayer PCB. Jun So Pak, Jingook Kim
.....
-Jason
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Lee Ritchey
Sent: Monday, October 29, 2007 5:17 PM
To: Steve Weir
Cc: Monji.Jabori@xxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR2 2-slot design preference...
Steve,
I have that paper and have read it. It does not corellate from the
tests
made to any real EMI failures. It just shows that ground stitching
results in a difference. There is a claim that this helpes solve a
problem
with a real product, but no data was presented. (There are many such
claims by EMI "Gurus" about their rules of thumb that turn out to be
just
that and this paper shows one, the 20H rule for one.)=20
Again, show me a real failure from cavity resonances, either functional
or
EMI not a simulation.
Truman used to say there are lies, damn lies and statistics. In our
profession there are lies, damn lies and unvalidated simulations, and,
no,
that paper does not demonstrate a direct correlation between the things
simulated and real failures, just before and after differences.
Lee
> [Original Message]
> From: steve weir <weirsi@xxxxxxxxxx>
> To: <leeritchey@xxxxxxxxxxxxx>
> Cc: <Monji.Jabori@xxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 10/29/2007 10:27:21 AM
> Subject: [SI-LIST] Re: DDR2 2-slot design preference...
>
> Lee, the case at issue was a GND-GND cavity, but applies equally well=20
> for mixed voltages. The physics are indisputable. The issue is how
bad=20
> does the problem have to be before we get: a) EMI radiation, and EFT
/=20
> ESD susceptibility, or b) signal integrity issues.=20
>
> The good news is that until we get to ultrafast edge rates the simple=20
> remedy for the GND-GND case is simply stitch with sufficient density.
> That is becoming tougher for GND-VCC cavities, but can still be done
in=20
> many cases. It depends on just how much energy one wants injects into
> the cavity and what the spectrum of that energy looks like.
>
> For an example of a real-life case where adding stitching fixed a real
> problem get a hold of EMC2 / Ansoft paper delivered in Santa Clara
just=20
> last week. There you will see good correlation between both the
models=20
> and the measurements demonstrating the phenomenon. In their case the=20
> stitch was good enough for signaling but was generating an EMI issue.
>
> In the past few years the speed and accuracy of various simulation=20
> methods has improved immensely. This permits designers to play
what-if=20
> and get excellent performance without becoming slaves to ad-hoc rules.
>
> Best Regards,
>
>
> Steve.
>
> Lee Ritchey wrote:
> > I have heard many times about cavity resonances between power and
ground
> > planes being the source of problems. However, I have yet to see any
clear
> > proof that such things happen and I have never seen a product fail
from
> > this in the design of 3000+ PCBs. Could those who claim this
happens
> > please supply some evidence of this? Not simulations, but actual
measured
> > results and not a statement that the last place it happened was at a
client
> > who has an NDA in place that prevents revealing the data.
> >
> > Lee Ritchey
> >
> >
> > =20
> >> [Original Message]
> >> From: steve weir <weirsi@xxxxxxxxxx>
> >> To: <Monji.Jabori@xxxxxx>
> >> Cc: <si-list@xxxxxxxxxxxxx>
> >> Date: 10/27/2007 2:09:16 PM
> >> Subject: [SI-LIST] Re: DDR2 2-slot design preference...
> >>
> >> Jabori, the issue in each case will be the resonant frequency of
the
GND=20
> >> - GND cavity. Stitch the cavity with an adequate via density to
get
the=20
> >> resonance well above your signal energy and either topology can be
made=20
> >> to work well.
> >>
> >> Steve.
> >> Jabori, Monji wrote:
> >> =20
> >>> Hi Experts,
> >>> =20
> >>>
> >>> I am looking at two designs for a 2-slot DDR2-800 memory system.
One
is
> >>> a butterfly design and the other has the slot on opposite sides of
the
> >>> motherboard (top and bottom).
> >>>
> >>> I am looking at the GND reference for both designs and have the
> >>> following question knowing that I have to use GND referenced
layers
for
> >>> each DDR2 channel.
> >>>
> >>> =20
> >>>
> >>> For a butterfly design, my traces on an 8-layer design will flow
from
> >>> the memory controller via 2 internal layers with 2 different GND
layers,
> >>> i.e., one slot will have to change GND reference while the other
will
> >>> not.
> >>>
> >>> =20
> >>>
> >>> In an opposite 2-slot design, however, we can make the traces that
go
to
> >>> each internal layer have the same GND reference as the DIMM that
is
> >>> closer to it. For example, the Top DIMM will have the same GND
reference
> >>> (L2) as its channel traces coming on L3 while the Bottom DIMM will
have
> >>> its GND reference (L7) as its channel traces coming on L6.
> >>>
> >>> =20
> >>>
> >>> Having said the above, would you guys prefer one design over
another
> >>> from an Signal Integrity point of view??
> >>>
> >>> =20
> >>>
> >>> Thanks in advance.
> >>>
> >>> =20
> >>>
> >>> Monji
> >>>
> >>> =20
> >>>
> >>> =20
> >>>
> >>>
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> >> --=20
> >> Steve Weir
> >> Teraspeed Consulting Group LLC=20
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> Steve Weir
> Teraspeed Consulting Group LLC=20
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