[SI-LIST] Re: DDR2 2-slot design preference...
- From: Jory McKinley <jory_mckinley@xxxxxxxxx>
- To: Scott McMorrow <scott@xxxxxxxxxxxxx>
- Date: Wed, 31 Oct 2007 13:06:45 -0700 (PDT)
Hello Scott,
But do we get the full wave (harmonics of) effect of the signal if the entire
structure (via/trace/cavity) is electrically short compared to the edge rates
we are passing through regardless of the data pattern of the signal? I would
say no since any energy injected by the signal up to the 5th harmonic would not
excite the structure above by definition. This may be a somewhat unrealistic
case today however not so some years back......
Back to reality.......As mentioned it seems to me today that a well contained
signal path may not be enough to fully contain the energy generated. The
problem I see today is that not only are the edge rates blazing but the fact
that full wave physics have to be applied at all discontinuities
(vias/connectors/pkg) along the path in order to get a complete picture of
signal energy. These discontinuities can couple energy into cavities or other
structures which should be understood.
Basic question: Assume you are tasked with getting information from one point
to another on just one lane of traffic. You are given a very simple
PWR-SIG-GND stackup and given zero discontinuities (assume perfectly matched
package/conn to signal trace) along the path from drvr to rcvr. The only other
requirement is that the trace has to be 10" or longer and you are given only a
50ps edge rate driver. Impossible to screw up?
-Jory
----- Original Message ----
From: Scott McMorrow <scott@xxxxxxxxxxxxx>
To: Jory McKinley <jory_mckinley@xxxxxxxxx>
Cc: vinu@xxxxxxxxx; eric@xxxxxxxxxxxxxxx; pritchard_jason@xxxxxxx;
si-list@xxxxxxxxxxxxx
Sent: Wednesday, October 31, 2007 11:24:25 AM
Subject: Re: [SI-LIST] Re: DDR2 2-slot design preference...
Jory
The electrical length of a via penetrating a cavity controls the amount
of energy injected into the cavity at any particular frequency. The
shorter the cavity crossing, the less energy injected, but energy is
nonetheless injected. An NRZ signal running a random pattern will
have signal energy drop off at a 20 dB/decade slope, until the Knee
frequency, where it drops off more rapidly. Up until you reach the
knee, you have to worry. As a result, there are significant signal
harmonics for even a 200 ps rise/fall time signal out to 1.75 GHz.
For example, a DDR2 500 memory system will have signal energy at 250
MHz, 750 MHz and 1.25 GHz. These are frequencies where it is quite
easy to build cavity resonances and parallel resonances in a PCB. Even
the slightest amount of energy coupled into the cavity is multiplied by
the large number of transitions that occur.
Let's say that 1 mV of noise is coupled from 1 DDR signal into a cavity
and rattles around. Now transition 128 signals simultaneously on a
double wide bus, and you've got 128 mV. What if the cavity resonates
at a particular frequency within the signal spectrum? If you excite
that frequency with a repetitive pattern, it is possible to pump up the
cavity, in which case you will easily see 2X, 4X or more of the
original injected noise, since planar cavities are not very lossy below
a few GHz.
If there are return path vias in the proximity of the signal vias, then
there is considerable energy containment. For ground-power
transitions that means that there needs to be ample bypass devices of
sufficiently low inductance to capture the energy, and the cavity
height needs to be sufficiently small to reduce the amount of energy
coupled. Unfortunately, it is sometimes the case that between memory
controllers and memory devices that additional signal transitions occur
without nearby bypass stitch vias or ground stitch vias. In that case,
significant energy can be coupled into these inadvertent resonant
circuits, resulting in increased power noise and signal crosstalk.
This is not generally a huge issue for differential signals, since
there is significant common mode cancellation, but can be a big problem
for large single-ended buses.
regards,
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Jory McKinley wrote:
Taking
a step back on this one...........How we look at a via structure
depends on the electrical length of the via structure versus the edge
rate of the signals traveling through the via structure. Most via's we
are dealing with have an electrical length in the 10ps - 30ps range.
The question is at what point can this via structure create potential
EMI/SI/resonance issues? It depends on the edge rate of the signals
traveling through the via structure. For example edge rates above
200ps hitting a typical via structure will encounter LRC effect given a
reasonable via ground return (If no via ground return we may excite
some cavity resonance). In reading most of this thread it would appear
that we are talking about edge rates in the 50ps - 150ps range where
full wave physics comes into play in a typical via structure.
-Jory
-----
Original Message ----
From: Scott McMorrow <scott@xxxxxxxxxxxxx>
To: vinu@xxxxxxxxx
Cc: eric@xxxxxxxxxxxxxxx; pritchard_jason@xxxxxxx; si-list@xxxxxxxxxxxxx
Sent: Tuesday, October 30, 2007 9:52:02 PM
Subject: [SI-LIST] Re: DDR2 2-slot design preference...
Vinu
Unfortunately you cannot apply a transmission line approximation to
signal and ground via sets. When a signal "turns the corner" and heads
down a signal via, a very complex set of interactions occur against all
of the local boundaries.
1) part of the wave detaches from the trace and surrounds the via.
2) simultaneously part of the wave detaches from the plane(s) it is
referenced to and heads down the rabbit hole through the via antipad
opening.
2a) For stripline, there is one signal via and two openings in the
plane, in which case the signal path splits and waves squirt up and
down
through the holes. When this happens the return path is majorly messed
up causing a conversion to the parallel plate mode of the cavity, with
a
circular wave front developing that propagates outward in all
directions
from the via in the center.
3) If there are ground vias across the cavity in the vicinity of the
signal via, then part of the cavity is shorted, and some of the
parallel
plate mode energy is returned back down towards the plane in the
direction of the signal travel.
4) One can simplify modeling of the behavior of a signal traveling on a
via as it passes through two planes in this manner, with a ground via
nearby, as the inductance and capacitance of this new transmission line
segment, but that is an oversimplification.
5) If you are transitioning single-ended signals through vias, and you
forget to stitch the planar cavities, you end up with all that
parallel-plate energy rattling around. Just like our friend, the
Wack-a-Mole(tm) it can and will pop up all over the place.
Eric is quite correct in his description. And he's quite correct about
his assumption about coaxial ground vias surrounding a signal via.
Take
a look at a good SMA launch pattern, or a good microstrip to via launch
pattern. There is more than impedance tuning going on.
Regards,
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Vinu Arumugham wrote:
> Eric,
>
> Unless I misunderstood, your description of the return via below
does not seem to be accurate.
> The signal via and return via(s) form a transmission line. One can
of course tune the impedance of the signal via by changing the spacing
and number of return vias. I don't think it is accurate to use the
lumped inductance value and say that the return via has a series
impedance of 6 ohm at 1GHz.
> The noise injected into the planes by the return via(s) should be
mostly canceled due to the noise injected by the signal via.
>
> "Keep in mind that a return via is not an ideal short. It has a
finite
> impedance. As a rough rule of thumb, its total inductance per
length is
> about 10 pH/mil. If the return via is 100 mils long, it has 1 nH
of total
> inductance. At 1 GHz, this is an impedance of 6 Ohms. If you have
1 return
> via per signal via, the ground bounce across it, which would be a
voltage
> source, injecting noise into the planes, would be about 10% of the
signal
> swing voltage."
>
> Thanks,
> Vinu
>
>
> Eric Bogatin wrote:
>
>> Guys-
>>
>> I'll add two observations to this discussion on planes, vias
and resonances.
>>
>> I've been doing a lot of via design and simulation work with a
3D planar
>> tool. I've had to re-adjust my intuition about the role of
adjacent return
>> vias and noise injection into cavities.
>>
>> As previously noted, the efficiency of injecting noise into
the plane to
>> plane cavity is related to the impedance of the cavity, which,
to first
>> order is about the spacing between the planes. The thinner the
dielectric,
>> the lower the impedance, and the less coupled energy driving
the plane
>> resonances.
>>
>> You get far more reduction in coupling to the cavity mode by
thinner
>> dielectric than by adding the return via. If the spacing
between the planes
>> is thin, there is less vertical distance to couple between and
the plane
>> impedance is lower.
>>
>> In a large board, there will always be adjacent planes in the
return path
>> with a large spacing and this is the pair where cavity
resonances will be
>> excited.
>>
>> Secondly, having an adjacent return via does not suppress the
coupling into
>> the cavity. It reduces it by maybe 50%, depending on the
spacing to the
>> signal via and its length. It is not enough to eliminate the
noise coupling
>> into the plane to just have a return via adjacent to the
signal via. You may
>> need a few. How many do you need? Of course, the answer is "it
depends."
>>
>> The rule of thumb is best articulated by my good friend Frank
Schonig who
>> says, "A lot is good, more is better and too much is just
right." I haven't
>> done the analysis, but I suspect that the more coaxial the
return via
>> arrangement looks to the signal via, the less total inductance
in the return
>> path and the less the radiated coupling into the plane to
plane cavity
>> resonance.
>>
>> Of course it is not practical to add 4 return vias around each
signal via,
>> unless you are doing a very low density, high isolation board,
like a test
>> board or a load board. Everything else is going to be a
compromise.
>>
>> If you are not going to do a detailed 3D planar simulation of
the return
>> plane stack up and the return via configuration to simulate
how much
>> insertion loss you loose into the planes, you will want to add
design
>> margin, like by adding vias along the edge, and multiple
return vias in
>> close proximity to the signal vias.
>>
>> Keep in mind that a return via is not an ideal short. It has a
finite
>> impedance. As a rough rule of thumb, its total inductance per
length is
>> about 10 pH/mil. If the return via is 100 mils long, it has 1
nH of total
>> inductance. At 1 GHz, this is an impedance of 6 Ohms. If you
have 1 return
>> via per signal via, the ground bounce across it, which would
be a voltage
>> source, injecting noise into the planes, would be about 10% of
the signal
>> swing voltage.
>>
>> --eric
>>
>>
>> **************************************
>> Dr. Eric Bogatin, President
>> Bogatin Enterprises, LLC
>> Setting the Standard for Signal Integrity Training
>> 26235 w 110th terr
>> Olathe, KS 66061
>> v: 913-393-1305
>> f: 913-393-0929
>> c:913-424-4333
>> e:eric@xxxxxxxxxxxxxxx
>> www.BeTheSignal.com
>> Spring 2008 Signal Integrity Training Institute
>> EPSI, SIAA, BBDP
>> April 7-11, 2008, San Jose, CA
>> ****************************************
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
>> Behalf Of pritchard_jason@xxxxxxx
>> Sent: Tuesday, October 30, 2007 1:58 PM
>> To: Chris.Cheng@xxxxxxxx; si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: DDR2 2-slot design preference...
>>
>> Yes 1 ground via was placed directly next to each the signal
vias on the
>> test board. They were 100 ohm vias. Unfortunately it kept the
impedance
>> low at the edges of the via structure where the grounds were
placed. You
>> would need more ground vias to truly pin it down. We did one
simulation
>> with them taken out to show how it got worse.=20
>>
>> I would imagine voltage planes are more often the culprit for
>> resonances. They may be only used to supply power at one
location on the
>> board and then are routed to the rest of the design as a signal
>> reference. These planes typically don't have capacitors placed
across
>> the whole design. If you did have capacitors across the whole
design you
>> may only have a limited frequency range in which that may be
effective.=20
>>
>> -Jason
>>
>>
>>
>> -----Original Message-----
>> From: Chris Cheng [mailto:Chris.Cheng@xxxxxxxx]=20
>> Sent: Tuesday, October 30, 2007 2:40 PM
>> To: pritchard, jason; si-list@xxxxxxxxxxxxx
>> Subject: RE: [SI-LIST] Re: DDR2 2-slot design preference...
>>
>> Before I started I have to say I am also a big fan of ground
via
>> stitching around edges of PCB.
>> That said. In your experiment, did you provide ground return
current
>> vias near your differential pair transition via ? One can
easily design
>> an experiment where return current path is denied (no ground
vias near
>> the signal vias) and it is forced to return through plane
coupling (i.e..
>> to justify thin core capacitance planes) or your via stitching
(to
>> contain the large EMI radiation field). Neither is the correct
solution
>> to the problem which is lack of return current vias.
>> Another thing to consider is in real live non-backplane PCB's,
there are
>> tens of thousands of ground vias by IC's and passive components
>> sprinkled around the PCB, it will be hard to find a large
piece of
>> via-less plane to start your resonance.
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx
>> [mailto:si-list-bounce@xxxxxxxxxxxxx]On
Behalf Of
>> pritchard_jason@xxxxxxx
>> Sent: Tuesday, October 30, 2007 10:32 AM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: DDR2 2-slot design preference...
>>
>>
>> I contributed to the paper, so I'll try and shed some light on
what was
>> in it...
>>
>> The purpose of the paper was to explain how high frequency
energy can
>> travel across a PCB and radiate from PCB edges or end up in
areas you
>> didn't expect it to be.=3D20
>>
>> If you spend a little time in the lab taking EMI measurements
then you
>> will find out that if you take any board with high speed
serial links
>> with via transitions or stripline routing, and measure around
the edge
>> of the PCB you will almost always find energy there. The
question I
>> always had was, how did it get there? I have been doing SI for
many
>> years so I typically thought about problems in 2 dimensions.
The problem
>> with EMI is it's 3 dimensional. It is sometimes difficult to
predict how
>> energy will travel. The first step is knowing the mechanisms
in which
>> energy gets diverted and spread out across the PCB.=3D20
>>
>> The first thing we did was set-up simple experiments in
SI-Wave to try
>> and figure out what was going on. We created simplified etch
layouts of
>> the real board that was having problems. We soon came to the
conclusion
>> that via transitions were exciting resonances on the PCB. What
we
>> determined was that the size of your reference plane and the
resultant
>> cavity resonances created between 2 planes caused energy to
travel in
>> the direction of the resonances when excited by via
transitions. This
>> loss of energy to the planes can also be seen in the
s-parameters of the
>> etch. That is essentially the first half of the paper.=3D20
>>
>> We then went into the lab. The experiments were done on a
backplane test
>> board. It only had ground planes. We chose this board because
it had SMA
>> connections and allowed us the flexibility to apply whatever
input we
>> wanted. It also had the same etch/via structures of our
problem board,
>> and proves the point that it doesn't matter if its power or
ground. All
>> you need is 2 metal pieces to create a cavity resonator.=3D20
>>
>> The simulations and lab measurements proved that you could
predict where
>> emissions would occur on a PCB. Did this experiment actually
solve a
>> real problem? Indirectly. Once we knew what mechanisms allowed
energy to
>> go to unwanted places on a PCB you can change the layout to
accommodate
>> this. One solution is to use via stitching along the edge of
the PCB to
>> reduce the impedance so that it cant radiate. This was
implemented
>> because the board slipped into metal clips at the edges of the
PCB. If
>> you can squelch the noise before it gets to the metal clips
you can
>> reduce the amount of energy directly coupled to the chassis.
Another
>> solution would be to make sure your return path impedance is
very low
>> along all of your high speed signals which is very difficult
in high
>> density boards.=3D20
>>
>> You could consider via fencing along the edge of a PCB a "rule
of
>> thumb", but it's a useful one because I have yet to see anyone
capable
>> of looking at a PCB and tell me how the energy is going to
travel across
>> the PCB, couple, and radiate. This is not a 2D SI problem its
3D.
>> Obviously you could put the work in and simulate it, but that
is often
>> time consuming and not available to most people.=3D20
>>
>> We were going to present the REAL board results at design con
in
>> February but it wasn't in the cards this year.=3D20
>>
>> I am not an EMI "guru". I just wanted to understand what is
happening.
>> Just because you haven't seen it doesn't mean it doesn't
exist.=3D20
>>
>> References:=3D20
>> * Reducing Simultaneous switching noise and emi on
ground/power planes
>> by dissipative edge termination. Istvan
>> * EMI mitigation with multilayer Power Bus Stacks and via
stitching of
>> reference planes. Xiaoning ye, David M. Hockanson, Min Li,.....
>> * Radiated Emission from a multilayer PCB with traces placed
between
>> power/ground planes. Takashi Harada, Hideki Sasaki, Toshihide
Kuriyama
>> * Reduction in radiated emission by symmetrical power-ground
layer
>> stack-up pcb no open edge. Satoru Haga, Ken Nakano, Osamu
Hashimoto
>> * The Radiation of a rectangular power bus structure at
multiple cavity
>> mode resonances. Marco Leone
>> * Coupling of through hole signal via to power/ground
references and
>> excitation of edge radiation in multilayer PCB. Jun So Pak,
Jingook Kim
>> .....
>>
>> -Jason
>>
>>
>>
>>
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