Hi Peter, A cavity is a cavity, regardless of its size, but the modal resonance frequencies do scale with the size and material properties. Large ri= gid boards tend to be much bigger than traditional microwave cavities, and the PCB dielectric material scales the frequencies down by anothe= r factor of two or so. This is the reason for lower resonance frequenc= ies. Another boundary constraint is that PCB planes tend to be much closer to each other than how big they are, so vertical resonances can mostl= y ignored. Regards, Istvan Peter S=F8rensen wrote On 10/30/07 10:23,: >Hi Everyone >Very existing to see a power palne resonance discussion between a lo= t of=20 >the well known experts. >I have a problem understanding the use of the word cavity together w= ith=20 >GND-PWR resonance in PCBs. >I believe that cavity resonance is somethink that will only occure a= t=20 >very high frequencies =3D many GHz which are irrelevant in normal P= CBs. >Could someone perhaps clarify? > >However when it comes to resonance problems in power planes I believ= e we=20 >have a relevant problem. >Power and GND (or GND -GND) planes forms a capacitor, via's connecti= ng=20 >to larger components caps and/or ICs has inductance and together the= y=20 >form a parallel resonance. >In most PCBs the power plane is so big that the parallel resonance i= s=20 >below 100MHz. Below 100MHz a number of parallel via's and decoupling= =20 >caps will form a low impedance and kill the resonance. >However in some designs you may have an IC running on a core supply= =20 >voltage that differs from the general supplies used. This voltage ma= y=20 >only get a very small plane like 1-2 square inch. (We all try to= =20 >minimize cost and complexity so we have multiple powers in each powe= r plane. >According to my simulations and an actual experience a resonance of= =20 >between 200-1000MHz is formed between the plane cap and the via's= =20 >inductance. >If the single IC's using this core has a core clock at or close to t= he=20 >parallel resonance a huge AC voltage may be seen on the power plane.= =20 >Again depending on whether the chips draws an AC current on its core= =20 >frequency. >Again I can not provide solid actual evidence. I can only say that t= he=20 >problem was solve in a new PCB where the power plane of this core= =20 >voltage was enlarged about 10 times in area. >As far as I remember we did add more decoupling caps so that spoils = some=20 >of the proof. But the AC voltage was reduce somethink like 10 times= =20 >while the added capacity was less than 100%. > >At present I am working on a design where I have many different volt= ages=20 >and only two power planes. So I will get small planes with a one or = two=20 >IC loads. These IC's has core frequencies of 400 and 600 MHz where= =20 >simulations show that I may have these parallel resonances. Adding m= ore=20 >power planes will add significant cost, so I can not do this if not = needed. > >As we are a small company it is impossible to get information on the= AC=20 >current load from the IC's we are using. I was wondering if it is= =20 >possible to measure the current without making a complex PCB? > >Other solutions could be to choose decoupling caps with serial reson= ance=20 >at the core frequency but tolerances on values makes it an unsure wa= y=20 >for production, even if it works on prototypes. > >Best >Peter S=F8rensen > > > > > > > >istvan novak wrote: > =20 > >>Lee, Orin, >> >>I see two general points in this thread that I want to comment on: >> >>1) Requesting proof that a given solution or the lack of it causes= =20 >>system failure sounds like a reasonable request, but with complex= =20 >>scenarios, like any kind of noise in the power distribution network= , we=20 >>may not see that proof publicly. If there is a product failure, th= e=20 >>company would not be happy to show all of the details about the des= ign,=20 >>necessary to get a convincing proof. There is a more generic reaso= n=20 >>also: with most noise phenomena, let it be signal integrity, power= =20 >>integrity or EMI, there are always multiple contributors, and event= ually=20 >>it is their constructive or destructive interference, which may cra= sh a=20 >>system. So picking one out of the many and asking whether that= =20 >>particular contributor breaks the system or not, is not realistic: = we=20 >>can trade most of these components and make one bigger, if we reduc= e=20 >>others. Therefore, showing and proving that a technique or solutio= n=20 >>does reduce a component IS a proof to me, unless of course the valu= e was=20 >>so low to start with that we can neglect it. If we have proof that= a=20 >>contributor can be reduced in a cost effective way, from that point= on=20 >>it is the designer's task to weigh in the necessary factors and to = make=20 >>a decision. >>2) PDN resonances dampened by chips: yes, it certainly can happen, = but=20 >>any reasonable power distribution network should have much lower= =20 >>impedance than the impedance of its load(s). So a chip can and wil= l=20 >>dampen (and detune) plane resonances primarily if there is no (or= =20 >>insufficient) bypassing present on the planes. With a decent worki= ng=20 >>PDN in place, we cant really count on the chip's impedance to dampe= n=20 >>resonances. You can find measured data from real boards and system= s in=20 >>Chapter 9 of the book: Frequency-Domain Characterization of Power= =20 >>Distribution Systems, Artech House, 2007. >> >>Regards, >> >>Istvan Novak >> >> >> >>Lee Ritchey wrote: >> >> =20 >> =20 >> >>>Steve, >>> >>>I have that paper and have read it. It does not corellate from th= e tests >>>made to any real EMI failures. It just shows that ground stitchi= ng >>>results in a difference. There is a claim that this helpes solve = a problem >>>with a real product, but no data was presented. (There are many s= uch >>>claims by EMI "Gurus" about their rules of thumb that turn out to = be just >>>that and this paper shows one, the 20H rule for one.)=20 >>> >>>Again, show me a real failure from cavity resonances, either funct= ional or >>>EMI not a simulation. >>> >>>Truman used to say there are lies, damn lies and statistics. In = our >>>profession there are lies, damn lies and unvalidated simulations, = and, no, >>>that paper does not demonstrate a direct correlation between the t= hings >>>simulated and real failures, just before and after differences. >>> >>>Lee >>> >>> >>>=20 >>> >>> =20 >>> =20 >>> >>>>[Original Message] >>>>From: steve weir <weirsi@xxxxxxxxxx> >>>>To: <leeritchey@xxxxxxxxxxxxx> >>>>Cc: <Monji.Jabori@xxxxxx>; <si-list@xxxxxxxxxxxxx> >>>>Date: 10/29/2007 10:27:21 AM >>>>Subject: [SI-LIST] Re: DDR2 2-slot design preference... >>>> >>>>Lee, the case at issue was a GND-GND cavity, but applies equally = well=20 >>>>for mixed voltages. The physics are indisputable. The issue is = how bad=20 >>>>does the problem have to be before we get: a) EMI radiation, and= EFT /=20 >>>>ESD susceptibility, or b) signal integrity issues.=20 >>>> >>>>The good news is that until we get to ultrafast edge rates the si= mple=20 >>>>remedy for the GND-GND case is simply stitch with sufficient dens= ity. =20 >>>>That is becoming tougher for GND-VCC cavities, but can still be d= one in=20 >>>>many cases. It depends on just how much energy one wants injects= into=20 >>>>the cavity and what the spectrum of that energy looks like. >>>> >>>>For an example of a real-life case where adding stitching fixed a= real=20 >>>>problem get a hold of EMC2 / Ansoft paper delivered in Santa Clar= a just=20 >>>>last week. There you will see good correlation between both the = models=20 >>>>and the measurements demonstrating the phenomenon. In their case= the=20 >>>>stitch was good enough for signaling but was generating an EMI is= sue. >>>> >>>>In the past few years the speed and accuracy of various simulatio= n=20 >>>>methods has improved immensely. This permits designers to play w= hat-if=20 >>>>and get excellent performance without becoming slaves to ad-hoc r= ules. >>>> >>>>Best Regards, >>>> >>>> >>>>Steve. >>>> >>>>Lee Ritchey wrote: >>>> =20 >>>> >>>> =20 >>>> =20 >>>> >>>>>I have heard many times about cavity resonances between power an= d ground >>>>>planes being the source of problems. However, I have yet to see= any >>>>> =20 >>>>> >>>>> =20 >>>>> =20 >>>>> >>>clear >>>=20 >>> >>> =20 >>> =20 >>> >>>>>proof that such things happen and I have never seen a product fa= il from >>>>>this in the design of 3000+ PCBs. Could those who claim this ha= ppens >>>>>please supply some evidence of this? Not simulations, but actua= l >>>>> =20 >>>>> >>>>> =20 >>>>> =20 >>>>> >>>measured >>>=20 >>> >>> =20 >>> =20 >>> >>>>>results and not a statement that the last place it happened was = at a >>>>> =20 >>>>> >>>>> =20 >>>>> =20 >>>>> >>>client >>>=20 >>> >>> =20 >>> =20 >>> >>>>>who has an NDA in place that prevents revealing the data. >>>>> >>>>>Lee Ritchey >>>>> >>>>> >>>>>=20 >>>>> =20 >>>>> >>>>> =20 >>>>> =20 >>>>> >>>>>>[Original Message] >>>>>>From: steve weir <weirsi@xxxxxxxxxx> >>>>>>To: <Monji.Jabori@xxxxxx> >>>>>>Cc: <si-list@xxxxxxxxxxxxx> >>>>>>Date: 10/27/2007 2:09:16 PM >>>>>>Subject: [SI-LIST] Re: DDR2 2-slot design preference... >>>>>> >>>>>>Jabori, the issue in each case will be the resonant frequency o= f the >>>>>> =20 >>>>>> >>>>>> =20 >>>>>> =20 >>>>>> >>>GND=20 >>>=20 >>> >>> =20 >>> =20 >>> >>>>>>- GND cavity. Stitch the cavity with an adequate via density t= o get >>>>>> =20 >>>>>> >>>>>> =20 >>>>>> =20 >>>>>> >>>the=20 >>>=20 >>> >>> =20 >>> =20 >>> >>>>>>resonance well above your signal energy and either topology can= be >>>>>> =20 >>>>>> >>>>>> =20 >>>>>> =20 >>>>>> >>>made=20 >>>=20 >>> >>> =20 >>> =20 >>> >>>>>>to work well. >>>>>> >>>>>>Steve. >>>>>>Jabori, Monji wrote: >>>>>> =20 >>>>>> =20 >>>>>> >>>>>> =20 >>>>>> =20 >>>>>> >>>>>>>Hi Experts, >>>>>>> >>>>>>> >>>>>>>I am looking at two designs for a 2-slot DDR2-800 memory syste= m. One >>>>>>> =20 >>>>>>> >>>>>>> =20 >>>>>>> =20 >>>>>>> >>>is >>>=20 >>> >>> =20 >>> =20 >>> >>>>>>>a butterfly design and the other has the slot on opposite side= s of the >>>>>>>motherboard (top and bottom). >>>>>>> >>>>>>>I am looking at the GND reference for both designs and have th= e >>>>>>>following question knowing that I have to use GND referenced l= ayers >>>>>>> =20 >>>>>>> >>>>>>> =20 >>>>>>> =20 >>>>>>> >>>for >>>=20 >>> >>> =20 >>> =20 >>> >>>>>>>each DDR2 channel. >>>>>>> >>>>>>> >>>>>>> >>>>>>>For a butterfly design, my traces on an 8-layer design will fl= ow from >>>>>>>the memory controller via 2 internal layers with 2 different G= ND >>>>>>> =20 >>>>>>> >>>>>>> =20 >>>>>>> =20 >>>>>>> >>>layers, >>>=20 >>> >>> =20 >>> =20 >>> >>>>>>>i.e., one slot will have to change GND reference while the oth= er will >>>>>>>not. >>>>>>> >>>>>>> >>>>>>> >>>>>>>In an opposite 2-slot design, however, we can make the traces = that go >>>>>>> =20 >>>>>>> >>>>>>> =20 >>>>>>> =20 >>>>>>> >>>to >>>=20 >>> >>> =20 >>> =20 >>> >>>>>>>each internal layer have the same GND reference as the DIMM th= at is >>>>>>>closer to it. For example, the Top DIMM will have the same GND >>>>>>> =20 >>>>>>> >>>>>>> =20 >>>>>>> =20 >>>>>>> >>>reference >>>=20 >>> >>> =20 >>> =20 >>> >>>>>>>(L2) as its channel traces coming on L3 while the Bottom DIMM = will >>>>>>> =20 >>>>>>> >>>>>>> =20 >>>>>>> =20 >>>>>>> >>>have >>>=20 >>> >>> =20 >>> =20 >>> >>>>>>>its GND reference (L7) as its channel traces coming on L6. >>>>>>> >>>>>>> >>>>>>> >>>>>>>Having said the above, would you guys prefer one design over a= nother >>>>>>> =20 >>>>>>> =20 >>>>>>> >>>>>>>from an Signal Integrity point of view?? >>>>>> =20 >>>>>> =20 >>>>>> >>>>>>>Thanks in advance. >>>>>>> >>>>>>> >>>>>>> >>>>>>>Monji >>>>>>> =20 >>>>>>> >>>>>>> =20 >>>>>>> =20 >>>>>>> >>>=20 >>> >>> =20 >>> =20 >>> ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu