Hello all, I have a SDRAM connected to a controller. The SDRAM operates at 133MHz. I am using hyperlynx for analysis. I am also using timing designer to check the setup and hold time margin From Hyperlynx I want to derive the delays due to transmission line and apply those delays to timing designer I wanted to know the procedure for doing that. Should I compensate for the flight time and what are all the data that I should use from hyperlynx simulation to add to the signal delay in timing designer to accurately calculate the time margin Can I use batch simualtion to simulate bunch of addr/data lines thanks in advance subramani ___________________________________________________________ Yahoo! Answers - Got a question? Someone out there knows the answer. Try it now. http://uk.answers.yahoo.com/ ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu