[SI-LIST] Free Webinar about Co-Design b/w IC and Package for Power Integrity
- From: "Patrick Lam" <plam@xxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 1 Oct 2007 15:05:21 -0700
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Hi All,
Apache and Optimal will have a free webinar about IC and Package design =
for Power Integrity. Please see the registration info. and details =
below.=20
Topic : Towards True Co-Design: Bridging the Gap between IC and Package =
Design for Power Integrity=20
=20
Overview:=20
For many years, the need for chip-package co-design to rapidly meet =
increasingly tight signal and power integrity (SI/PI) constraints in a =
cost-effective way has been more than obvious. Increasing functional =
integration, higher speed input-output signaling, and low-power design =
techniques have continued to exacerbate this need. "Co-design" as it is =
practiced today, however, is often little more than isolated design of =
the chip and package followed by co-optimization across product =
generations. Existing EDA tools and analysis techniques address SI/PI =
issues at the package and chip levels, but not with an integrated =
approach, which is needed for accurate and actionable tradeoff analyses.
In this webinar, we explore the symmetrical use of package-aware chip =
analysis and chip-aware package analysis to address true IC-Package =
co-design. The chip-package core power delivery network (PDN) is =
analyzed for static IR drop and dynamic voltage drop (DvD), pointing to =
design improvements through floor planning, decoupling capacitance, and =
wire-bonding design. Including the I/O subsystem as well enables =
assessment of timing metrics (e.g. jitter) and simultaneous switching =
output (SSO) noise, pointing to design improvements available through =
voltage domain partitioning and impedance control. Due to the unique =
awareness of both the chip and package, tradeoffs in chip versus package =
complexity emerge as a new design freedom to meet performance and cost =
demands.
What will be covered:=20
In this educational webinar, Apache and Optimal will detail the =
methodology and technology used for integrated IC-Package co-design. The =
webinar will include several design examples to illustrate system design =
issues and their resolution. Specifically, the webinar will discuss:
* Impact of package on chip power integrity=20
* Methodology for power analysis with consideration of package impact=20
* Technology for generating core power delivery network=20
* Use of chip power model in package design=20
Who should attend:=20
* Physical designers working on designs especially at 90nm or below=20
* Signal integrity engineers=20
* Package design engineers=20
* Design methodology and design architects=20
Presenters:=20
=20
Emre Kulali, Senior Applications Engineer, Apache Design Solutions =
Currently, Emre is the lead applications engineer for Apache's newly =
introduced Sentinel product line, addressing the IC-Package power and =
signal integrity challenges. Prior to joining Apache in 2004, Mr. Kulali =
held various engineering positions with OEA International Inc. and =
CoWare Inc. Mr. Kulali holds a Bachelors of Science in Physics & =
Mathematics from St. Lawrence University, N.Y. and a Masters of Science =
in Engineering Management from Santa Clara University.
=20
Mark Kowalski, Senior Applications Engineer, Optimal Corporation Mark is =
directly engaged with a number of clients advising on the combined use =
of Apache's RedHawk and Sentinel tools with Optimal's PowerGrid and =
PakSI-E. Dr. Kowalski has a broad background in the use of computational =
field solvers in solving practical engineering problems in areas =
including high-speed signaling, remote sensing, and high energy physics. =
He has published extensively in the peer-reviewed literature in this =
area and is an elected member of USNC Commission B. Under support from =
the National Science Foundation to investigate the role of field solvers =
in medical (MRI) safety, he earned the Ph.D. in electrical engineering =
from the University of Illinois at Urbana-Champaign in 2002. Since then, =
he has served in various engineering and program management roles under =
support from the U.S. Departments of Energy, Homeland Security, and =
Defense at the Stanford Linear Accelerator Center (SLAC) and L-3 =
Communications.
=20
You can register for the webinar at:=20
HYPERLINK =
http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=3Dapach=
e_oct0907 =
http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=3Dapach=
e_oct0907
Regards
Patrick Lam
Optimal Corp.
6980 Santa Teresa Blvd. #100
San Jose, Ca 95119
Tel: 408-363-6301
No virus found in this outgoing message.
Checked by AVG Free Edition.=20
Version: 7.5.488 / Virus Database: 269.13.37/1042 - Release Date: =
10/1/2007 6:59 PM
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