Posts for si-list, 03-2015

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  1. » [SI-LIST] Anyone opened the eye, at 28 Gbps, for any of the 802.3bj working group's channels?, David Banas
  2. » [SI-LIST] Trying to find an old article, Doug Brooks
  3. » [SI-LIST] characteristic impedance of the waveport, jun zhang
  4. » [SI-LIST] Mastering High Speed Serial Tech Class -, Ransom Stephens
  5. » [SI-LIST] Free Power Integrity Analysis Workshops in March from ANSYS, Margaret Schmitt
  6. » [SI-LIST] Looking for an ME ..., Bill Hargin (Nan Ya, USA)
  7. » [SI-LIST] Looking for an ME ... (Reformatted), Bill Hargin (Nan Ya, USA)
  8. » [SI-LIST] SI intern - Cisco Systems SJ, Mike Sapozhnikov (msapozhn)
  9. » [SI-LIST] ANN: Rel. v1.4 of PyBERT., David Banas
  10. » [SI-LIST] IDT Shanghai is looking for a SI engineer, Feng Wu
  11. » [SI-LIST] IEEE EMC Santa Clara Valley Chapter Monthly Meeting 3/10 @SIEMIC in Milpitas, Eriko Yamato
  12. » [SI-LIST] Tuesday March 10th 2015 IEEE EMC meeting with Bruce Archambeault -->note change of venue !, Giuseppe Selli (giselli)
  13. » [SI-LIST] PCB LAYER STACKUP, Suresh R S
  14. » [SI-LIST] How to Reasonably Correlate The SAS 12G Signal Interface?, 鄭銘賢
  15. » [SI-LIST] reduce xtalk thru polarity reversal, Chen, Sherman
  16. » [SI-LIST] Re: Tap settings on IBIS AMI models, David Banas
  17. » [SI-LIST] Opportunity at MathWorks -- March 2015, Mark Reichelt
  18. » [SI-LIST] Serdes Rx Jitter Tolerance, Conrad Herse
  19. » [SI-LIST] IBIS 5.0 model for DDR3 component, GORAL Benoit
  20. » [SI-LIST] Reg ESD protection on user switches, Vinod Kumar
  21. » [SI-LIST] Reg SI Simulation for high speed SERDES, Vinod Kumar
  22. » [SI-LIST] Good YouTube presentation on de-embedding, Alfred P. Neves
  23. » [SI-LIST] modeling PDN including die level, eric silist
  24. » [SI-LIST] Reference planes contuniety and margininality, Igal Fridman
  25. » [SI-LIST] 10th International Workshop on the EMC of Integrated Circuits - Call for Papers, Kieran O' Leary
  26. » [SI-LIST] European IBIS Summit at SPI 2015 - First Call for Presentations and Participation, Mirmak, Michael
  27. » [SI-LIST] ANSYS Hosting free Power Integrity Workshop in Austin, TX, March 26th, Margaret Schmitt
  28. » [SI-LIST] Sr. Project Signal Integrity Engr Opening,
  29. » [SI-LIST] Minimum length for SERDES, bala
  30. » [SI-LIST] IBIS model for High Impedance State, 이상호
  31. » [SI-LIST] Hyperlynx Far-end crosstalk simulation issue, 廖梦婷
  32. » [SI-LIST] Hyperlynx far end crosstalk simulation issue, 163
  33. » [SI-LIST] Registration is Now Open for the 9th Central PA Signal Integrity Symposium, April 17, 2015, ALDO W MORALES
  34. » [SI-LIST] Published worst case channel/x-talk models for DDR4 design purposes?, David Banas
  35. » [SI-LIST] Request for feedback on published article., David Banas
  36. » [SI-LIST] test, Yogesh Sharma (ysharma)
  37. » [SI-LIST] Please Post - Cisco Sr. Hardware Engineer, Steven Goloskov -X (sgolosko - RANDSTAD NORTH AMERICA LP at Cisco)
  38. » [SI-LIST] Why are PCIe card edges beveled and DIMMs aren't?, Loyer, Jeff
  39. » [SI-LIST] Eric Bogatin Workshop May 12-13, Longmont, CO - Never be intimidated by S-parameters again, Don DeGroot
  40. » [SI-LIST] New College Grad Packaging Design Engineer Opening at Xilinx, Ray Anderson
  41. » [SI-LIST] Cisco Job Opening - Senior Signal Integrity Engineer, Steven Goloskov -X (sgolosko - RANDSTAD NORTH AMERICA LP at Cisco)
  42. » [SI-LIST] Current Distribution, bala
  43. » [SI-LIST] AC timing analysis, Parveen
  44. » [SI-LIST] Re: AC timing analysis, Brad Griffin
  45. » [SI-LIST] DesignCon papers posted, Istvan Novak
  46. » [SI-LIST] Channel deterministic jitter, Ralph Wilson
  47. » [SI-LIST] Experienced Signal Integrity Engineer, Yogesh Sharma (ysharma)
  48. » [SI-LIST] PDN Resistance, Marc SI
  49. » [SI-LIST] Review of Steven Sandler's new book on Power Integrity, Ken Wyatt