[SI-LIST] Re: Current Distribution

  • From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
  • To: balaseven@xxxxxxxxx, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Sun, 29 Mar 2015 11:47:47 -0400

Hi Bala,

Again, assuming that the simulation tool and its setup is correct, yes, 
the location of the stitching vias can make a huge different in the 
current density through the vias.  In a real scenario you have many 
parallel current filaments representing the total current flow.  At DC, 
current in the lowest resistance path will carry most of the current.  
If you move a via (leaving the other vias unchanged) closer to a current 
source or current sink, it will carry more current.  The same is true 
the opposite way: you observe the current through a particular via and 
you dont move it, while you move the other vias around: as the other 
vias move further away, likely the current in the via you are observing, 
is going up.

Simulation setup also matters: commercial tools may offer you a helping 
hand setting up sources and sinks on multi-pin devices.  You need to be 
careful with such options, because such solutions may enforce a 
equipotential area over those pins, which artificially increases the 
current density near the edges and corners of the connection block. 
'Artificially increases' means the tool correctly calculates the answer 
to the scenario we told the tool to simulate, but in real life multi-pin 
devices will not be really equipotential.

Regards,

Istvan Novak
Oracle



On 3/29/2015 7:18 AM, bala r wrote:
> Thanks Patrick for your detailed explanation.
> Do you think the location of the stitching via impacts current density.For 
> example,when I have these vias a little away from the source the density was 
> more.When I juxtapose the source pin and stitching via or when I have these 
> on the path between source and sink the density was better.I think this is 
> happening because of the inadequacy of the simulation tool.What do you think?
> Regards
> bala
>
> -----Original Message-----
> From: "Carrier, Patrick" <Patrick_Carrier@xxxxxxxxxx>
> Sent: ‎27-‎03-‎2015 09:43 PM
> To: "balaseven@xxxxxxxxx" <balaseven@xxxxxxxxx>; "si-list@xxxxxxxxxxxxx" 
> <si-list@xxxxxxxxxxxxx>
> Subject: RE: [SI-LIST] Current Distribution
>
> Hi Bala--
> I assume you are talking about DC currents?
> You mention the "shortest path", but really what you are after is the path of 
> least resistance, which includes multiple paths in parallel.  (When talking 
> about AC, it is the path of least impedance, which usually translates to the 
> path of least inductance).
>
> If you want to understand how current is going to divide between each layer, 
> it might be a good exercise to try and break the structure down into its 
> components and draw a circuit with a bunch of resistors to see how much 
> current goes where.  As Istvan indicated, the via connections play a big 
> part.  If the resistance through your via(s) is really high, not much current 
> is going to travel through the extra plane layers.  It is like adding a large 
> resistor in parallel with a smaller resistor: the parallel combination will 
> result in a slightly lower total resistance, but little current is going to 
> pass through that larger resistor.
>
> If you want to develop some intuition on how big the resistances are in your 
> circuit, luckily, the math for DC Drop problems is pretty easy.  Resistance 
> is resistivity divided by area multiplied by length.
> The resistivity of copper is rho = 1.724x10^-8 ohm-m.  If you convert this to 
> mils, it is 6.787x10^-4 ohm-mil.
> So, for a via, the resistance would be: rho * length / [pi*(drill size / 2)^2 
> - pi*((drill size - (plating thickness*2))/2)^2]
> For an 8-mil drill via with 0.5-oz (0.7-mil) plating that goes all the way 
> through a 82-mil board, the resistance of that via would be 3.47mOhm end to 
> end.
> As a point of reference, a comparable plane shape would be a 1-inch-wide 
> plane shape 4 inches long on 0.5-oz. copper, which has a resistance of 
> 3.88mOhm.
>
> If you have a simulation tool that allows you to modify things like the 
> number of vias and their locations, you can experiment to see how changes to 
> the vias can affect the current distribution.
>
> --Pat
>   
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
> Behalf Of bala
> Sent: Friday, March 27, 2015 7:58 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Current Distribution
>
> Hi All,
>
> I have a three identical PCB plane for a particular voltage rail and the load 
> consumes 10 amps. Since the planes are identical each plane will carry 1/3rd 
> of the total current? Is this correct? Or the shortest path takes the entire 
> current always .How the current are distributed in PCB when we have multiple 
> planes on multiple layers for same voltage. When I do current density 
> analysis all three shapes shows violation and when I add one more shape on 
> another layer to bring density down the density on surviving three layers did 
> not change. As we added additional layer for this rail, we should see some 
> difference in the layer density. As the tool takes the total current (10 
> Amps, instead of 1/3rd) on each layer the density is more, so we should allot 
> the current carefully? Am I correct? Any suggestions?
>
> Regards
> bala
>
>
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