[SI-LIST] Re: AC timing analysis
- From: "Parveen" <parveen.rao@xxxxxxxxxxxx>
- To: "'Brad Griffin'" <bgriffin@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sun, 29 Mar 2015 16:07:52 +0530
Thanks for reply.
I am doing for RGMII interface , CMOS parallel interface and DDR2 . for that I
need , how much tolerance between data and strobe trace( source synchronous )
. how to calculate this.
From: Brad Griffin [mailto:bgriffin@xxxxxxxxxxx]
Sent: Saturday, March 28, 2015 8:19 PM
To: 'parveen.rao@xxxxxxxxxxxx'; 'si-list@xxxxxxxxxxxxx'
Subject: RE: [SI-LIST] AC timing analysis
Suggest Greg Edlund's book on thus topic.
http://www.amazon.com/gp/aw/d/B00132S6X2/ref=tmm_kin_title_0?ie=UTF8
<http://www.amazon.com/gp/aw/d/B00132S6X2/ref=tmm_kin_title_0?ie=UTF8&sr=&qid>
&sr=&qid
Brad
-----Original Message-----
From: Parveen [parveen.rao@xxxxxxxxxxxx]
Sent: Friday, March 27, 2015 11:56 PM Pacific Standard Time
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] AC timing analysis
Hi All,
Do anybody is having idea about AC timing analysis , for interfacing to high
speed interface . How to do this . ?
With Best Regards,
Parveen Rao
VVDN Technologies Pvt. Ltd.
Cell : +91-9468287074 | Skype : parveenrao23
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