[SI-LIST] Re: Reference planes contuniety and margininality
- From: Yun Chase <chase@xxxxxxxxxxx>
- To: "Chris.Cotton@xxxxxxxxxxx" <Chris.Cotton@xxxxxxxxxxx>, "'ifridman@xxxxxxxxxxxx'" <ifridman@xxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 16 Mar 2015 18:41:22 -0700
Adding one more note to what Chris mentioned below...
Newly integrated with Allegro, Cadence Sigrity SPEED2000 also has a layout
checker based on electrical rules and field solutions that can check for
non-ideal reference plane-aware impedance and crosstalk for all critical nets.
For more info please refer to:
http://www.cadence.com/rl/Resources/datasheets/Cadence_Sigrity_Speed2000_DS.pdf
Regards,
Chase
----------------------
Yun Chase | SPB Sr. Staff Application Engineer | Cadence
P: 508.565.8080 www.cadence.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Cotton, Chris
Sent: Monday, March 16, 2015 10:25 AM
To: 'ifridman@xxxxxxxxxxxx'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Reference planes contuniety and margininality
Cadence Allegro (i.e., 16.6) has a "Segments Over Voids" check which generates
a report of such disccontinuities. I have not used this extensively but more
for sanity checks. You may want to try this.
Chris
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Igal Fridman
Sent: Monday, March 16, 2015 6:18 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Reference planes contuniety and margininality
Hi folks,
I think everyone is familiar with importance of reference part continuity and
sufficient margin from signal edge (due to manufacturing miss-registration,
return path etc.).
The layout inspection usually is done visually.
Could you advise me on existence of the feature in any CAD or dedicated scripts
that checks it?
Thank you,
Igal Fridman,
SIE
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