[SI-LIST] Re: PDS analysis?
- From: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>
- To: "steve weir" <weirsi@xxxxxxxxxx>
- Date: Mon, 31 Mar 2008 20:35:41 -0700
Commenting on the original question, it would seem that the value of PDS
analysis depends on the characteristics of the devices that are mounting on
this hypothetical "industry standard layout" PCB. If the devices also follow
"industry standard" conventions for their chip / die PDS, then one might have
some degree of confidence that terminal problems are not likely. OTOH, if these
devices are demanding in their current requirements then PDS analysis may be
critical. Every case is different, of course, and experience with various cases
may allow one to have a feel for when the "industry standard" is sufficient and
when PDS analysis is called for. I'm not advocating avoiding PDS analysis and I
agree that it is always safer to fully simulate designs before building them.
-Ivor
-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]
Sent: Saturday, March 29, 2008 2:17 PM
To: Bowden, Ivor
Cc: Gil Simsic [IEEE]; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: PDS analysis?
Ivor, you are welcome.
Your informal survey results are interesting. The heartburn that I get
with "just follow these xx rules" is that ultimately the idea that any
practice(s) applied without analysis will work is a truism. Sooner or
later the design characteristics that result from a given practice will
not meet the actual requirements. The only way that we can know is to
determine requirements and then design against them. And while some of
the expensive tools are nice and can provide value, a more than adequate
analysis can be done without spending a quarter million on tools. OTOH
getting good measurements out of a PDN that encompass the entire set of
operating conditions can present a significant challenge. And by the
time that is doable the design has already been tooled.
Yes, I've fixed and/or cost reduced any number of designs by changing
some capacitor values. The location of a given value capacitor doesn't
tend to be nearly as critical as some publications might have you
think. My best advice is to really get a handle on spatial effects.
Once a design engineer really understands the spatial considerations of
a PDN, zeroing in on a viable, cost competitive design becomes like
riding a bike.
Regards,
Steve.
Bowden, Ivor wrote:
>
> Hi Steve,
>
> Thank you for your reply! This is the type of answer I was looking
> for. I'm not "going anywhere with this", not advocating any particular
> position, just looking for information about ramifications of typical
> design practices.
>
> I know that PDS analysis tools are not as ubiquitous as simulation /
> crosstalk tools, and many companies, especially smaller ones, tend to
> skip this step, instead relying on experience with past designs. I was
> wondering how frequently these designs have problems due to
> sub-optimal PDS, the nature of the problems, and the resolutions. For
> instance, have you seen many cases where going to smaller value bypass
> caps at specific points improved a broken circuit?
>
> I apologize for not doing more research before posting the question.
> I'm sure I can find a variety of examples with enough searching.
> Mainly I was looking for opinion, preferably backed by knowledge.
>
> As sort of an informal survey, it was interesting to note that the off
> list replies tended more towards "for typical boards PDS isn't needed
> if proper rules are followed", generally backed up with statistics of
> successful boards not PDS analyzed, while the on list replies tend to
> be more of the "always do PDS analysis" flavor.
>
> Again, not going anywhere with this. I agree that the safest design
> practice is to fully simulate the design, including PDS.
>
> Ivor
Say you have a typical PCB with modern technology mix of CPU, DSP, DDR, GIGE,
PCIE, etc. Say it is a multi-layer stackup in the form of GND-SIG-SIG-GND sets,
with the power distribution centered in the stackup as solid ground plane -
split power plane - split power plane - solid ground plane, using 1oz copper
and 3.5 mil dielectric. Assuming the split power planes utilize sufficient area
to keep the point to point inductance and resistance to reasonable values, and
0.1uF ceramic bypass caps are evenly placed at device pins, and bulk
capacitance is placed as needed, would there be reason to expect any problems,
such as plane resonance, etc? If so, what would be the observable real world
manifestations, in terms of circuit performance and power pins scope waveforms?
Would there be significant advantage to analyzing this PDS, or should following
this "industry standard practice" for PCB PDS be sufficient to expect robust
behavior?
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