[SI-LIST] Re: PDS analysis?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>
- Date: Sat, 29 Mar 2008 14:17:08 -0700
Ivor, you are welcome.
Your informal survey results are interesting. The heartburn that I get
with "just follow these xx rules" is that ultimately the idea that any
practice(s) applied without analysis will work is a truism. Sooner or
later the design characteristics that result from a given practice will
not meet the actual requirements. The only way that we can know is to
determine requirements and then design against them. And while some of
the expensive tools are nice and can provide value, a more than adequate
analysis can be done without spending a quarter million on tools. OTOH
getting good measurements out of a PDN that encompass the entire set of
operating conditions can present a significant challenge. And by the
time that is doable the design has already been tooled.
Yes, I've fixed and/or cost reduced any number of designs by changing
some capacitor values. The location of a given value capacitor doesn't
tend to be nearly as critical as some publications might have you
think. My best advice is to really get a handle on spatial effects.
Once a design engineer really understands the spatial considerations of
a PDN, zeroing in on a viable, cost competitive design becomes like
riding a bike.
Regards,
Steve.
Bowden, Ivor wrote:
>
> Hi Steve,
>
>
>
> Thank you for your reply! This is the type of answer I was looking
> for. I'm not "going anywhere with this", not advocating any particular
> position, just looking for information about ramifications of typical
> design practices.
>
>
>
> I know that PDS analysis tools are not as ubiquitous as simulation /
> crosstalk tools, and many companies, especially smaller ones, tend to
> skip this step, instead relying on experience with past designs. I was
> wondering how frequently these designs have problems due to
> sub-optimal PDS, the nature of the problems, and the resolutions. For
> instance, have you seen many cases where going to smaller value bypass
> caps at specific points improved a broken circuit?
>
>
>
> I apologize for not doing more research before posting the question.
> I'm sure I can find a variety of examples with enough searching.
> Mainly I was looking for opinion, preferably backed by knowledge.
>
>
>
> As sort of an informal survey, it was interesting to note that the off
> list replies tended more towards "for typical boards PDS isn't needed
> if proper rules are followed", generally backed up with statistics of
> successful boards not PDS analyzed, while the on list replies tend to
> be more of the "always do PDS analysis" flavor.
>
>
>
> Again, not going anywhere with this. I agree that the safest design
> practice is to fully simulate the design, including PDS.
>
>
>
> Ivor
>
>
>
>
>
> -----Original Message-----
> From: steve weir [mailto:weirsi@xxxxxxxxxx]
> Sent: Saturday, March 29, 2008 3:00 AM
> To: Bowden, Ivor
> Cc: Gil Simsic [IEEE]; si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: PDS analysis?
>
>
>
> Ivor, you can find examples in papers by people like Larry, Istvan, and
>
> books that are out there. But, I am not sure where you are going with
>
> this. Since terms like "well fed" are ambiguous, I don't know what
>
> example you are looking for or to what purpose. My sense is that you
>
> have a belief that if one follows some ambiguous "industry practices"
>
> that the PDN will usually "work fine". Undefined engineering leads to
>
> undefined results. If you want predictable results then: Define the
>
> requirements and engineer to them.
>
>
>
> We can characterize components to determine their actual power delivery
>
> requirements. Once known we can easily demonstrate failures that result
>
> when we don't meet those requirements. It is also easy to demonstrate
>
> what different PDN practices do to the impedance profile under any
>
> particular set of controlled circumstances we wish to create.
>
>
>
> If you want to see resonance effects for yourself then: Design some
>
> board following one of the popular ad-hoc rules. If for example you
>
> design a board with one 0402 capacitor every two square inches and the
>
> plane cavity is 4mil FR406 on layers 2/3, the bypass to cavity PRF will
>
> land around 330MHz depending on how you do your vias. If the planes are
>
> deeper in the board that frequency will just go down. Then get yourself
>
> a programmable clock generator and use it to drive some device like a
>
> PLD or FPGA with a bunch of outputs simultaneously in a simple 1-0-1-0
>
> sequence while you monitor the power supply planes with a decent scope.
>
> Just step frequency until the bit rate / 2 excites the lowest parallel
>
> resonance in the power system. After that experiment see if your
>
> feelings about what works fine are still the same.
>
>
>
> Steve
>
>
>
> Bowden, Ivor wrote:
>
> > Hi Gil,
>
> >
>
> >
>
> > Thanks for sharing.
>
> >
>
> >
>
> >
>
> > By "real world" I do not mean rules of thumb and shortcuts, I mean
> examples. I expect that most folks on this list, especially those for
> whom SI is primary activity, can demonstrate examples of operational
> failures due to bad board layout. I also know that a large number of
> designs never get PDS analysis, yet work fine. I'm interested in
> typical modern technology designs that are laid out in standard
> industry practice: contiguous ground planes, tandem heavy split power
> planes not used as return reference, plenty of properly located bypass
> caps, etc that have operational failures which could have been
> pre-determined by PDS analysis, and if so, how did that operational
> failure manifest? For example, it would be interesting to see a scope
> (or simulation) snap shot of the voltage measured directly across vias
> to contiguous well fed planes as a device current requirement
> approaches the planes resonant frequency. And I mean a real device,
> not a hypothetical entity tuned to instigat
>
> > e the problem.
>
> >
>
> >
>
> >
>
> > -Ivor
>
> >
>
> >
>
> >
>
> > -----Original Message-----
>
> > From: Gil Simsic [IEEE] [mailto:gsimsic.ieee@xxxxxxxxxxxxx]
>
> > Sent: Friday, March 28, 2008 1:08 PM
>
> > To: Bowden, Ivor; si-list@xxxxxxxxxxxxx
>
> > Subject: Re: [SI-LIST] Re: PDS analysis?
>
> >
>
> >
>
> >
>
> > Ivor
>
> >
>
> >
>
> >
>
> > I am involved in design since 1993, and have numerous of successful
> designs
>
> >
>
> > under my belt. (I know - not very humble...)
>
> >
>
> >
>
> >
>
> > In one way or another I worked and learned from SI leaders (aka - gurus)
>
> >
>
> > like Lee Ritchey, Istvan Novak, Eric Bogatin, Scott McMorrow and Howard
>
> >
>
> > Johnson (and others that due to a senior moment I did not mention here -
>
> >
>
> > sorry) I gratefully owe my knowledge to them.
>
> >
>
> >
>
> >
>
> > by the way - all I tried to do is to learn about "real world picture".
>
> >
>
> >
>
> >
>
> > My greatest lesson is - there are no short cuts and no rule of thumbs. I
>
> >
>
> > read daily emails on this list that prove this point over and over again.
>
> >
>
> >
>
> >
>
> > And than again I might misunderstand you...
>
> >
>
> > If the by 'real world' you refer to 'rules of thumbs' and 'short
> cuts', I
>
> >
>
> > will strongly recommend you to shy away from that 'real world'. I really
>
> >
>
> > think that any design as hypothetic or rhetorical as it is, needs
> analysis
>
> >
>
> > (the subject of your email is PDS analysis...).
>
> >
>
> >
>
> >
>
> > Most of the SI phenomena are frequency depended.
>
> >
>
> >
>
> >
>
> > You said - * I'm more interested in answers like "you might see a
> waveform
>
> >
>
> > of xxx characteristics across the bypass capacitor". *
>
> >
>
> > My answer - "you might see a waveform of xxx characteristics across the
>
> >
>
> > bypass capacitor". ;-)
>
> >
>
> > How can one attempt giving you any 'ball-park' numbers for a frequency
>
> >
>
> > dependent component with out knowing what the frequency parts are?
>
> >
>
> >
>
> >
>
> > Good luck!
>
> >
>
> >
>
> >
>
> > Gil
>
> >
>
> > ----- Original Message -----
>
> >
>
> > From: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>
>
> >
>
> > To: <si-list@xxxxxxxxxxxxx>
>
> >
>
> > Sent: Friday, March 28, 2008 12:11 PM
>
> >
>
> > Subject: [SI-LIST] Re: PDS analysis?
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >> Hi,
>
> >>
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >> I'd like to thank everyone who replied so far, off and on the list. I
>
> >>
>
> >
>
> >
>
> >> emphasize that this is a rhetorical question, it doesn't represent any
>
> >>
>
> >
>
> >
>
> >> specific product. I also emphasize that I'm interested more in the
> "real
>
> >>
>
> >
>
> >
>
> >> world observation" part. Instead of answers like "your power plane may
>
> >>
>
> >
>
> >
>
> >> have a resonance at xxx frequency", I'm more interested in answers like
>
> >>
>
> >
>
> >
>
> >> "you might see a waveform of xxx characteristics across the bypass
>
> >>
>
> >
>
> >
>
> >> capacitor". Also, this question is more about power distribution than
>
> >>
>
> >
>
> >
>
> >> signal return path. All answers appreciated.
>
> >>
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >> -Ivor
>
> >>
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >> ________________________________
>
> >>
>
> >
>
> >
>
> >
>
> >
>
> >> From: Bowden, Ivor
>
> >>
>
> >
>
> >
>
> >> Sent: Friday, March 28, 2008 7:24 AM
>
> >>
>
> >
>
> >
>
> >> To: si-list@xxxxxxxxxxxxx
>
> >>
>
> >
>
> >
>
> >> Subject: PDS analysis?
>
> >>
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >> Hi SI Experts,
>
> >>
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >> Say you have a typical PCB with modern technology mix of CPU, DSP, DDR,
>
> >>
>
> >
>
> >
>
> >> GIGE, PCIE, etc. Say it is a multi-layer stackup in the form of
>
> >>
>
> >
>
> >
>
> >> GND-SIG-SIG-GND sets, with the power distribution centered in the
> stackup
>
> >>
>
> >
>
> >
>
> >> as solid ground plane - split power plane - split power plane - solid
>
> >>
>
> >
>
> >
>
> >> ground plane, using 1oz copper and 3.5 mil dielectric. Assuming the
> split
>
> >>
>
> >
>
> >
>
> >> power planes utilize sufficient area to keep the point to point
> inductance
>
> >>
>
> >
>
> >
>
> >> and resistance to reasonable values, and 0.1uF ceramic bypass caps are
>
> >>
>
> >
>
> >
>
> >> evenly placed at device pins, and bulk capacitance is placed as needed,
>
> >>
>
> >
>
> >
>
> >> would there be reason to expect any problems, such as plane resonance,
>
> >>
>
> >
>
> >
>
> >> etc? If so, what would be the observable real world manifestations, in
>
> >>
>
> >
>
> >
>
> >> terms of circuit performance and power pins scope waveforms? Would
> there
>
> >>
>
> >
>
> >
>
> >> be significant advantage to analyzing this PDS, or should following
> this
>
> >>
>
> >
>
> >
>
> >> "industry standard practice" for PCB PDS be sufficient to expect robust
>
> >>
>
> >
>
> >
>
> >> behavior?
>
> >>
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >> Thanks,
>
> >>
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >
>
> >> Ivor Bowden
>
> >>
>
> >
>
> >
>
> >
>
> >
>
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> >>
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> >
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> >
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> >
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> >
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> >
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> >
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> >
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> >
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> >
>
> >
>
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> --
>
> Steve Weir
>
> Teraspeed Consulting Group LLC
>
> 121 North River Drive
>
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