[SI-LIST] Re: PDS analysis?

Hi Gil,
 

Thanks for sharing.

 

By "real world" I do not mean rules of thumb and shortcuts, I mean examples. I 
expect that most folks on this list, especially those for whom SI is primary 
activity, can demonstrate examples of operational failures due to bad board 
layout. I also know that a large number of designs never get PDS analysis, yet 
work fine. I'm interested in typical modern technology designs that are laid 
out in standard industry practice: contiguous ground planes, tandem heavy split 
power planes not used as return reference, plenty of properly located bypass 
caps, etc that have operational failures which could have been pre-determined 
by PDS analysis, and if so, how did that operational failure manifest? For 
example, it would be interesting to see a scope (or simulation) snap shot of 
the voltage measured directly across vias to contiguous well fed planes as a 
device current requirement approaches the planes resonant frequency. And I mean 
a real device, not a hypothetical entity tuned to instigate the problem.

 

-Ivor

 

-----Original Message-----
From: Gil Simsic [IEEE] [mailto:gsimsic.ieee@xxxxxxxxxxxxx] 
Sent: Friday, March 28, 2008 1:08 PM
To: Bowden, Ivor; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: PDS analysis?

 

Ivor

 

I am involved in design since 1993, and have numerous of successful designs 

under my belt. (I know - not very humble...)

 

In one way or another I worked and learned from SI leaders (aka - gurus) 

like Lee Ritchey, Istvan Novak, Eric Bogatin, Scott McMorrow and Howard 

Johnson (and others that due to a senior moment I did not mention here - 

sorry) I gratefully owe my knowledge to them.

 

by the way - all I tried to do is to learn about "real world picture".

 

My greatest lesson is - there are no short cuts and no rule of thumbs. I 

read daily emails on this list that prove this point over and over again.

 

And than again I might misunderstand you...

If the by 'real world' you refer to 'rules of thumbs' and 'short cuts', I 

will strongly recommend you to shy away from that 'real world'. I really 

think that any design as hypothetic or rhetorical as it is, needs analysis 

(the subject of your email is PDS analysis...).

 

Most of the SI phenomena are frequency depended.

 

You said - * I'm more interested in answers like "you might see a waveform 

of xxx characteristics across the bypass capacitor". *

My answer - "you might see a waveform of xxx characteristics across the 

bypass capacitor". ;-)

How can one attempt giving you any 'ball-park' numbers for a frequency 

dependent component with out knowing what the frequency parts are?

 

Good luck!

 

Gil

----- Original Message ----- 

From: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>

To: <si-list@xxxxxxxxxxxxx>

Sent: Friday, March 28, 2008 12:11 PM

Subject: [SI-LIST] Re: PDS analysis?

 

 

> Hi,

> 

> 

> I'd like to thank everyone who replied so far, off and on the list. I 

> emphasize that this is a rhetorical question, it doesn't represent any 

> specific product. I also emphasize that I'm interested more in the "real 

> world observation" part. Instead of answers like "your power plane may 

> have a resonance at xxx frequency", I'm more interested in answers like 

> "you might see a waveform of xxx characteristics across the bypass 

> capacitor". Also, this question is more about power distribution than 

> signal return path. All answers appreciated.

> 

> 

> 

> -Ivor

> 

> 

> 

> ________________________________

> 

> From: Bowden, Ivor

> Sent: Friday, March 28, 2008 7:24 AM

> To: si-list@xxxxxxxxxxxxx

> Subject: PDS analysis?

> 

> 

> 

> Hi SI Experts,

> 

> 

> 

> Say you have a typical PCB with modern technology mix of CPU, DSP, DDR, 

> GIGE, PCIE, etc. Say it is a multi-layer stackup in the form of 

> GND-SIG-SIG-GND sets, with the power distribution centered in the stackup 

> as solid ground plane - split power plane - split power plane - solid 

> ground plane, using 1oz copper and 3.5 mil dielectric. Assuming the split 

> power planes utilize sufficient area to keep the point to point inductance 

> and resistance to reasonable values, and 0.1uF ceramic bypass caps are 

> evenly placed at device pins, and bulk capacitance is placed as needed, 

> would there be reason to expect any problems, such as plane resonance, 

> etc? If so, what would be the observable real world manifestations, in 

> terms of circuit performance and power pins scope waveforms? Would there 

> be significant advantage to analyzing this PDS, or should following this 

> "industry standard practice" for PCB PDS be sufficient to expect robust 

> behavior?

> 

> 

> 

> Thanks,

> 

> 

> 

> Ivor Bowden

> 

> Senior Hardware Engineer

> 

> Curtiss-Wright Controls Embedded Computing

> 

> 10201 Wateridge Circle

> 

> Suite 300

> 

> San Diego, CA 92121

> 

> 858-452-0020 x 4405

> 

> ibowden@xxxxxxxxxxxxxxxxx

> 

> 

> 

> 

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_______________________________________________________________________
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solely for the use of the individual or entity to whom they are addressed. If 
you have reason to believe that you have received this e-mail in error, please 
notify the sender and destroy this email and any attached files. Please note 
that any views or opinions presented in this e-mail are solely those of the 
author and do not necessarily represent those of the Curtiss-Wright Corporation 
or any of its subsidiaries.  Documents attached hereto may contain technology 
subject to government export regulations. Recipient is solely responsible for 
ensuring that any re-export, transfer or disclosure of this information is in 
accordance with applicable government export regulations.  The recipient should 
check this e-mail and any attachments for the presence of viruses. 
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