[SI-LIST] Re: PDS analysis?

Dan,
 

Thank you for your reply. I know there have been studies contrasting lower 
value caps with via inductance. Are there cases, with adjacent thin dielectric 
power - gnd stickups, where changing 0.1uF ceramic bypass caps to lower values 
solved cases of dysfunctional operation?

 

-Ivor

 

-----Original Message-----
From: Dan Smith [mailto:Dan.Smith@xxxxxxxxx] 
Sent: Friday, March 28, 2008 8:56 AM
To: Bowden, Ivor; si-list@xxxxxxxxxxxxx
Subject: RE: PDS analysis?

 

Ivor,

 

With what you described below there could be problems.  These problems would be 
manifested as noise ripple on your VCC planes which will eat into your margins 
budget for Vih and Vil of your devices.  By placing only 0.1uf capacitors and 
no other values, you have only minimized your noise on your power planes at 
about 10mhz.

 

You can never eliminate your parallel resonance but adding additional 
capacitors will lower the overall inductance of the mounting capacitors which 
(when intersected with your plane capacitor) will lower the impedance holes 
somewhat and move them out higher in frequency.  But again, they will never be 
eliminated.

 

You should use more capacitor values for sure.

 

Dan

 

-----Original Message-----

From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Bowden, Ivor

Sent: Friday, March 28, 2008 7:24 AM

To: si-list@xxxxxxxxxxxxx

Subject: [SI-LIST] PDS analysis?

 

Hi SI Experts,

 

 

Say you have a typical PCB with modern technology mix of CPU, DSP, DDR, GIGE, 
PCIE, etc. Say it is a multi-layer stackup in the form of GND-SIG-SIG-GND sets, 
with the power distribution centered in the stackup as solid ground plane - 
split power plane - split power plane - solid ground plane, using 1oz copper 
and 3.5 mil dielectric. Assuming the split power planes utilize sufficient area 
to keep the point to point inductance and resistance to reasonable values, and 
0.1uF ceramic bypass caps are evenly placed at device pins, and bulk 
capacitance is placed as needed, would there be reason to expect any problems, 
such as plane resonance, etc? If so, what would be the observable real world 
manifestations, in terms of circuit performance and power pins scope waveforms? 
Would there be significant advantage to analyzing this PDS, or should following 
this "industry standard practice" for PCB PDS be sufficient to expect robust 
behavior?

 

 

 

Thanks,

 

 

 

Ivor Bowden

 

Senior Hardware Engineer

 

Curtiss-Wright Controls Embedded Computing

 

10201 Wateridge Circle

 

Suite 300

 

San Diego, CA 92121

 

858-452-0020 x 4405

 

ibowden@xxxxxxxxxxxxxxxxx

 

 

 

 

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