[SI-LIST] Re: PDS analysis?
- From: "Sinha, Snehamay" <snehamay@xxxxxx>
- To: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 28 Mar 2008 15:36:34 -0500
Ivor,
The behavior of the PDS depends on both the pcb and the device
properties. With the same pcb (board stackup, bypass capacitors) if the
devices on the board have high di/dt,then you will see higher voltage
drop than what you will observe if the di/dt for the devices is low.
My opinion is that you will need to analyze the pcb to ensure that your
power supply specs are met.
Regards,
Snehamay Sinha
DSP Design
Texas Instruments
Dallas TX 75243
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Bowden, Ivor
Sent: Friday, March 28, 2008 9:24 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PDS analysis?
Hi SI Experts,
=20
Say you have a typical PCB with modern technology mix of CPU, DSP, DDR,
GIGE, PCIE, etc. Say it is a multi-layer stackup in the form of
GND-SIG-SIG-GND sets, with the power distribution centered in the
stackup as solid ground plane - split power plane - split power plane -
solid ground plane, using 1oz copper and 3.5 mil dielectric. Assuming
the split power planes utilize sufficient area to keep the point to
point inductance and resistance to reasonable values, and 0.1uF ceramic
bypass caps are evenly placed at device pins, and bulk capacitance is
placed as needed, would there be reason to expect any problems, such as
plane resonance, etc? If so, what would be the observable real world
manifestations, in terms of circuit performance and power pins scope
waveforms? Would there be significant advantage to analyzing this PDS,
or should following this "industry standard practice" for PCB PDS be
sufficient to expect robust behavior?
=20
Thanks,
=20
Ivor Bowden
Senior Hardware Engineer
Curtiss-Wright Controls Embedded Computing
10201 Wateridge Circle
Suite 300
San Diego, CA 92121
858-452-0020 x 4405
ibowden@xxxxxxxxxxxxxxxxx
=20
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