[SI-LIST] Re: PDS analysis?

Snehamay,

Thank=20you=20for=20your=20reply!=20I'll=20agree,=20it=20is=20best=20to=20=
analyze=20the=20PDS.

-Ivor

-----Original=20Message-----
From:=20Sinha,=20Snehamay=20[mailto:snehamay@xxxxxx]=20
Sent:=20Friday,=20March=2028,=202008=201:37=20PM
To:=20Bowden,=20Ivor;=20si-list@xxxxxxxxxxxxx
Subject:=20RE:=20[SI-LIST]=20PDS=20analysis?

Ivor,
=20The=20behavior=20of=20the=20PDS=20depends=20on=20both=20the=20pcb=20and=
=20the=20device
properties.=20With=20the=20same=20pcb=20(board=20stackup,=20bypass=20capac=
itors)=20if=20the
devices=20on=20the=20board=20have=20high=20di/dt,then=20you=20will=20see=20=
higher=20voltage
drop=20than=20what=20=20you=20will=20observe=20if=20the=20di/dt=20for=20th=
e=20devices=20=20is=20low.
My=20opinion=20is=20that=20you=20will=20need=20to=20analyze=20the=20pcb=20=
to=20ensure=20that=20your
power=20supply=20specs=20are=20met.

Regards,
Snehamay=20Sinha
DSP=20Design
Texas=20Instruments
Dallas=20TX=2075243




-----Original=20Message-----
From:=20si-list-bounce@xxxxxxxxxxxxx=20[mailto:si-list-bounce@xxxxxxxxxxxx=
g]
On=20Behalf=20Of=20Bowden,=20Ivor
Sent:=20Friday,=20March=2028,=202008=209:24=20AM
To:=20si-list@xxxxxxxxxxxxx
Subject:=20[SI-LIST]=20PDS=20analysis?

Hi=20SI=20Experts,
=20

Say=20you=20have=20a=20typical=20PCB=20with=20modern=20technology=20mix=20=
of=20CPU,=20DSP,=20DDR,
GIGE,=20PCIE,=20etc.=20Say=20it=20is=20a=20multi-layer=20stackup=20in=20th=
e=20form=20of
GND-SIG-SIG-GND=20sets,=20with=20the=20power=20distribution=20centered=20i=
n=20the
stackup=20as=20solid=20ground=20plane=20-=20split=20power=20plane=20-=20sp=
lit=20power=20plane=20-
solid=20ground=20plane,=20using=201oz=20copper=20and=203.5=20mil=20dielect=
ric.=20Assuming
the=20split=20power=20planes=20utilize=20sufficient=20area=20to=20keep=20t=
he=20point=20to
point=20inductance=20and=20resistance=20to=20reasonable=20values,=20and=20=
0.1uF=20ceramic
bypass=20caps=20are=20evenly=20placed=20at=20device=20pins,=20and=20bulk=20=
capacitance=20is
placed=20as=20needed,=20would=20there=20be=20reason=20to=20expect=20any=20=
problems,=20such=20as
plane=20resonance,=20etc?=20If=20so,=20what=20would=20be=20the=20observabl=
e=20real=20world
manifestations,=20in=20terms=20of=20circuit=20performance=20and=20power=20=
pins=20scope
waveforms?=20Would=20there=20be=20significant=20advantage=20to=20analyzing=
=20this=20PDS,
or=20should=20following=20this=20"industry=20standard=20practice"=20for=20=
PCB=20PDS=20be
sufficient=20to=20expect=20robust=20behavior?

=20

Thanks,

=20

Ivor=20Bowden

Senior=20Hardware=20Engineer

Curtiss-Wright=20Controls=20Embedded=20Computing

10201=20Wateridge=20Circle

Suite=20300

San=20Diego,=20CA=2092121

858-452-0020=20x=204405

ibowden@xxxxxxxxxxxxxxxxx

=20


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