[SI-LIST] Re: PDS analysis?
- From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
- To: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>
- Date: Tue, 01 Apr 2008 09:03:28 -0400
Ivor,
There have been lots of comments and discussion following your posting. =
I would like to offer a few additional comments going back to your core=20
question: "Assuming the split power planes utilize sufficient area to=20
keep the point to point inductance and resistance to reasonable values,=20
and 0.1uF ceramic bypass caps are evenly placed at device pins, and bulk =
capacitance is placed as needed, would there be reason to expect any=20
problems, such as plane resonance, etc?"
- as always, it depends, but there are circumstances when such a simple=20
network works well. If you use only one value, 0.1uF, ceramics, this=20
falls into the "Big-V" type, and your best bet is to use similarly a=20
single value of bulk capacitor. By doing so you eliminated the=20
potential antiresonances among bulk capacitors (because there is only=20
one value) and among ceramic capacitors (because there is only one=20
value). Staying on the board, you are left with three potential problem =
areas: a) the DC source and bulk capacitor interface, b) bulk capacitor=20
and ceramic capacitor interface and c) ceramic capacitor to PCB=20
interface. For instance, if your impedance target is around 0.1 ohms=20
(may be good for typical rails with a few amperes current consumption),=20
you can use bulk capacitor(s) with 0.1 ohms ESR together with for=20
instance twenty to thirty 0.1uF ceramics. With typical ESR and ESL=20
values, this gives a nice interface between the bulk and ceramic=20
capacitors. Assuming a small plane puddle, this should be OK.
- the DC-source to bulk interface is an often overlooked problem area. =20
Too much bulk capacitance (too many uF and/or too low ESR) may drive the =
converter loop into instability, or may create startup problems. Too=20
little bulk capacitance may result in an antiresonance peaking above=20
your target impedance at low frequencies. There are good simulation=20
aids for converter chips, but hardly anything for complete DC-DC=20
converter modules. If you are willing to take the time to simulate the=20
state-averaged converter performance with your planned PDN, ask your=20
converter vendors; though they do not offer these simulators publicly,=20
some will make it available for you if you ask.
- the ceramic capacitor and plane interface has a few potential issues:=20
a) antiresonance between the static plane capacitance and inductances of =
bypass capacitors, b) modal resonances of planes and c) too much=20
inductance presented to active devices. These risk areas are=20
inter-related. For instance, using thick laminates makes solve a)=20
easier but solve c) harder and vice versa. Regarding b), your best bet=20
is to make component placement such that your plane-shape size is minimiz=
ed.
One additional comment about the stackup: having paralleled power stack=20
in the middle between ground planes is good for isolating power splits=20
from high-speed traces (no issues with traces crossing splits), but the=20
vertical coupling between the plane shapes above each other is very=20
strong at high frequencies: you need to make sure that you dont allow=20
vertical overlap between very noisy and very sensitive (supposedly=20
low-noise) rails.
The above are considerations of the primary PDN function, delivering=20
clean power to the chips. As Chris always points out, the return-path=20
function always needs to be looked even if on your board traces do not=20
reference power planes.. Our EMI-prevention goals are usually covered=20
in the regular PDN design process by suppressing plane resonances.
Regards,
Istvan Novak
SUN Microsystems
Bowden, Ivor wrote:
> Hi SI Experts,
> =20
>
> Say you have a typical PCB with modern technology mix of CPU, DSP, DDR,=
GIGE, PCIE, etc. Say it is a multi-layer stackup in the form of GND-SIG-=
SIG-GND sets, with the power distribution centered in the stackup as soli=
d ground plane - split power plane - split power plane - solid ground pla=
ne, using 1oz copper and 3.5 mil dielectric. Assuming the split power pla=
nes utilize sufficient area to keep the point to point inductance and res=
istance to reasonable values, and 0.1uF ceramic bypass caps are evenly pl=
aced at device pins, and bulk capacitance is placed as needed, would ther=
e be reason to expect any problems, such as plane resonance, etc? If so, =
what would be the observable real world manifestations, in terms of circu=
it performance and power pins scope waveforms? Would there be significant=
advantage to analyzing this PDS, or should following this "industry stan=
dard practice" for PCB PDS be sufficient to expect robust behavior?
>
> =20
>
> Thanks,
>
> =20
>
> Ivor Bowden
>
> Senior Hardware Engineer
>
> Curtiss-Wright Controls Embedded Computing
>
> 10201 Wateridge Circle
>
> Suite 300
>
> San Diego, CA 92121
>
> 858-452-0020 x 4405
>
> ibowden@xxxxxxxxxxxxxxxxx
> =20
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