[SI-LIST] Re: PDS analysis?

Hi Ivor

Say you have never heard of Faraday, Gauss and Ampere. Say we can defy 
physics - than you are good to go :-)
I hope it does not come across as a demeaning comment, I am just trying to 
make a point...

I would highly recommend to you reading Lee Ritchey's book "Right the first 
time". Lee has a very strong approach that there are NO 'rules of thumb' and 
nothing is 'simple' and I totally agree with him. I have few years of board 
and Si design and many of the Gurus on this list can vouch - nothing is 
really simple...

So what or where things can go wrong -
1. You did not tell us what is the Trise and Tfall of your signals, does 
0.35/Trise... ring any bells?
2. A thorough analysis of your PDS is needed for the "REAL" spectrum of your 
signals (see #1) (Look for Istvan Novak's book) and hence what C and how 
many will give you the target impedance of your PDS
3. Placement of Vias, traces components can affect tremendously - it sound 
like you have a loaded board... a 0.1 cap in the wrong place will not help, 
too many of them will create other issues...
4. Return path is a funky thing, and when you really thing you know it - 
think again, did you consider the vias... and the coupling between traces
5. What is the expected performance of this board - is it just a demo board 
where you can find a 'sweet spot' that it will work, (say xxxMHz and room 
temp) or is it a product that needs to be mounted in the Mojave desert or in 
Antarctica?


Last but not least -
If time and budget allowing it - just try it :-)
if you want to make 'Right the first time' some consideration is needed

Cheers

Gil



----- Original Message ----- 
From: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Friday, March 28, 2008 7:23 AM
Subject: [SI-LIST] PDS analysis?


> Hi SI Experts,
>
>
> Say you have a typical PCB with modern technology mix of CPU, DSP, DDR, 
> GIGE, PCIE, etc. Say it is a multi-layer stackup in the form of 
> GND-SIG-SIG-GND sets, with the power distribution centered in the stackup 
> as solid ground plane - split power plane - split power plane - solid 
> ground plane, using 1oz copper and 3.5 mil dielectric. Assuming the split 
> power planes utilize sufficient area to keep the point to point inductance 
> and resistance to reasonable values, and 0.1uF ceramic bypass caps are 
> evenly placed at device pins, and bulk capacitance is placed as needed, 
> would there be reason to expect any problems, such as plane resonance, 
> etc? If so, what would be the observable real world manifestations, in 
> terms of circuit performance and power pins scope waveforms? Would there 
> be significant advantage to analyzing this PDS, or should following this 
> "industry standard practice" for PCB PDS be sufficient to expect robust 
> behavior?
>
>
>
> Thanks,
>
>
>
> Ivor Bowden
>
> Senior Hardware Engineer
>
> Curtiss-Wright Controls Embedded Computing
>
> 10201 Wateridge Circle
>
> Suite 300
>
> San Diego, CA 92121
>
> 858-452-0020 x 4405
>
> ibowden@xxxxxxxxxxxxxxxxx
>
>
>
>
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