Posts for si-list, 04-2008

Browse: Last Month: 03-2008 Main Archive Page Next Month: 05-2008

» [SI-LIST] Webinar on chip-package co-design for power integrity -
» [SI-LIST] Re: Query on power noise sensitivity measurement problem -
» [SI-LIST] ADSL test question -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] Packaging Design Engineer Position at Altera Corporation -
» [SI-LIST] Re: Simulating TDR in HSPICE for single-ended trace -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] Re: Query on power noise sensitivity measurement problem -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: Query on power noise sensitivity measurement problem -
» [SI-LIST] Re: Query on power noise sensitivity measurement problem -
» [SI-LIST] Re: Query on power noise sensitivity measurement problem -
» [SI-LIST] Re: Query on power noise sensitivity measurement problem -
» [SI-LIST] Query on power noise sensitivity measurement problem -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Redistribution Layer -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Fwd: Need Franz Gisin Contact Info -
» [SI-LIST] Need Franz Gisin Contact Info -
» [SI-LIST] Thermal simulation -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] new posting to www.beTheSignal.com -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: Simulating TDR in HSPICE for single-ended trace -
» [SI-LIST] Re: Receiver Jitter Testing -
» [SI-LIST] Re: Termination schemes -
» [SI-LIST] Re: Difference between conducted and radiated emission ? -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: Termination schemes -
» [SI-LIST] Re: Receiver Jitter Testing -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: Receiver Jitter Testing -
» [SI-LIST] Re: Receiver Jitter Testing -
» [SI-LIST] Receiver Jitter Testing -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: Termination schemes -
» [SI-LIST] Re: What is the frequency range of the Stratix III cor e -
» [SI-LIST] Re: What is the frequency range of the Stratix III cor e -
» [SI-LIST] Re: What is the frequency range of the Stratix III cor e -
» [SI-LIST] Re: What is the frequency range of the Stratix III cor e -
» [SI-LIST] Re: What is the frequency range of the Stratix III cor e -
» [SI-LIST] Re: What is the frequency range of the Stratix III core -
» [SI-LIST] What is the frequency range of the Stratix III core -
» [SI-LIST] How to do optimization for minimum power delay product -
» [SI-LIST] Public Nokia Siemens Networks IBIS website online -
» [SI-LIST] Re: Termination schemes -
» [SI-LIST] Termination schemes -
» [SI-LIST] Thermal Simulation -
» [SI-LIST] Simulating TDR in HSPICE for single-ended trace -
» [SI-LIST] Re: difference b/w CM & DM noise -
» [SI-LIST] Re: difference b/w CM & DM noise -
» [SI-LIST] Re: difference b/w CM & DM noise -
» [SI-LIST] difference b/w CM & DM noise -
» [SI-LIST] Signal Integrity position available -
» [SI-LIST] USB Plugfest.. -
» [SI-LIST] Re: a question about IBIS package information -
» [SI-LIST] Re: Am I missing something on CM Impedance vs Diff Impedance -
» [SI-LIST] Re: Am I missing something on CM Impedance vs Diff Impedance -
» [SI-LIST] Am I missing something on CM Impedance vs Diff Impedance -
» [SI-LIST] Design Challenges: PI/SI & EMC Simulation -
» [SI-LIST] Re: a question about IBIS package information -
» [SI-LIST] How to determine the extraction frequency? -
» [SI-LIST] a question about IBIS package information -
» [SI-LIST] 答复: IBIS question -
» [SI-LIST] Re: IBIS question -
» [SI-LIST] Re: IBIS question -
» [SI-LIST] IBIS question -
» [SI-LIST] test -
» [SI-LIST] Re: Comparing layers on two artworks -
» [SI-LIST] Re: Comparing layers on two artworks -
» [SI-LIST] Re: Comparing layers on two artworks -
» [SI-LIST] Re: Comparing layers on two artworks -
» [SI-LIST] Re: Comparing layers on two artworks -
» [SI-LIST] Re: Comparing layers on two artworks -
» [SI-LIST] Re: Comparing layers on two artworks -
» [SI-LIST] Re: Comparing layers on two artworks -
» [SI-LIST] Re: Comparing layers on two artworks -
» [SI-LIST] Re: Comparing layers on two artworks -
» [SI-LIST] Re: Comparing layers on two artworks -
» [SI-LIST] How to define radial boundary conditions in CST MW STUDIO -
» [SI-LIST] Comparing layers on two artworks -
» [SI-LIST] Re: ppm related question -
» [SI-LIST] Re: ppm related question -
» [SI-LIST] Re: ppm related question -
» [SI-LIST] Re: ppm related question -
» [SI-LIST] ppm related question -
» [SI-LIST] Re: XrossTalk Magazine April Issue: Power Integrity -
» [SI-LIST] Manager of Package Engineering needed at AMCC in San Diego -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] -
» [SI-LIST] Package Design Automation Engineer openning at Altera Corporation -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] XrossTalk Magazine April Issue: Power Integrity -
» [SI-LIST] Principal SI Engineer opening at Apple -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] Re: Standard Cell Library Design -
» [SI-LIST] A Hspice question about current on W-element -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] Re: On-die caps for IO supply -
» [SI-LIST] On-die caps for IO supply -
» [SI-LIST] Standard Cell Library Design -
» [SI-LIST] 答复: A Hspice question about current on W-element -
» [SI-LIST] Re: return path -
» [SI-LIST] Re: return path -
» [SI-LIST] serdes device locking issues -
» [SI-LIST] A Hspice question about current on W-element -
» [SI-LIST] Re: return path -
» [SI-LIST] Re: return path -
» [SI-LIST] return path -
» [SI-LIST] Package Design Engineer Position at Altera Corporation -
» [SI-LIST] Re: Modeling of varactor in CMOS process Upto 10G -
» [SI-LIST] PCB trace resonances -
» [SI-LIST] Modeling of varactor in CMOS process Upto 10G -
» [SI-LIST] A Hspice question about current on W-element -
» [SI-LIST] IBIS seminar discount for IBIS members -
» [SI-LIST] Re: Measuring uV signals in PSRR test -
» [SI-LIST] Re: hierarchical schematic editor? -
» [SI-LIST] Re: hierarchical schematic editor? -
» [SI-LIST] Re: hierarchical schematic editor? -
» [SI-LIST] hierarchical schematic editor? -
» [SI-LIST] Measuring uV signals in PSRR test -
» [SI-LIST] Re: PDS analysis? -
» [SI-LIST] Biasing 1000 BaseT signals -
» [SI-LIST] Free HSPICE and IBIS Seminar in Boston Area Apr 7th -
» [SI-LIST] Re: PDS analysis? -
» [SI-LIST] Re: Frequency Spectrum of TIE -
» [SI-LIST] Re: PDS analysis? -
» [SI-LIST] Re: PDS analysis? -
» [SI-LIST] Re: Frequency Spectrum of TIE -
» [SI-LIST] Re: Frequency Spectrum of TIE -
» [SI-LIST] Re: DDR1 without VTT termination -
» [SI-LIST] Frequency Spectrum of TIE -
» [SI-LIST] Re: Do you ever measure any of the things you model? -
» [SI-LIST] Re: Do you ever measure any of the things you model? -
» [SI-LIST] Re: Do you ever measure any of the things you model? -
» [SI-LIST] Re: Do you ever measure any of the things you model? -
» [SI-LIST] Re: Do you ever measure any of the things you model? -
» [SI-LIST] Re: Do you ever measure any of the things you model? -
» [SI-LIST] Signal Integrity Symposium -
» [SI-LIST] Re: Do you ever measure any of the things you model? -
» [SI-LIST] Re: PDS analysis? -
» [SI-LIST] Re: PDS analysis? -
» [SI-LIST] Re: DDR1 without VTT termination -
» [SI-LIST] Re: PDS analysis? -
» [SI-LIST] DDR2 question -
» [SI-LIST] Re: PDS analysis? -
» [SI-LIST] Re: PDS analysis? -
» [SI-LIST] Re: PDS analysis? -
» [SI-LIST] Re: PDS analysis? -