[SI-LIST] Re: 90 degree bend
- From: Michael Brenneman <meb@xxxxxxxxxxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 02 Sep 2004 17:51:12 -0700
Hello Everyone,
I thought it may be appropriate to mention on this thread some work that
Ansoft has been doing with Xilinx on high speed channel modeling. For
those who have an in-depth interest, please visit
http://www.gigabitbackplanedesign.com to download the design kit which
includes a white paper and the Xilinx Virtex-II Pro X MK322 test board
channel model.
In the past, engineers often solved the physical layout effects separate
from the circuit, making it tedious and time consuming to investigate
bends and other structures quickly and easily. New technology has made
it possible to create parameterized EM discontinuity models and
dynamically link them into a full channel circuit (please refer to the
attached screen shot). This provides very fast exploration of the
physical effects of bends, vias, and other discontinuities on the
circuit or system. Furthermore, since the speed of EM solvers is
always a concern for circuit designers, the ability to interpolate
between previously solved EM data makes it possible to simulate changes
in "real time".
Lastly, previous work on the XFP consortium, Cray Computer, and other
work have indicated to us that 3D discontinuities (vias, connectors)
will usually be the bandwidth limiting factor in the channel. Effects
from bends may not be significant until the data rate reaches 10 Gbps or
faster.
Hope this is helpful.
best regards,
-mike
--
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Michael Brenneman
Ansoft Corporation
Application Engineering Manager
Western Region
5300 Stevens Creek Blvd.
Suite 650
San Jose, CA 95129
phone: 408-261-9095 x31
fax: 408-261-1245
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Ansoft Corporate Headquarters
Four Station Square
Suite 200
Pittsburgh, PA 15219
phone: 412-261-3200
fax: 412-471-9427
--------------------- http://www.ansoft.com ---------------------
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