[SI-LIST] Re: anti-resonance point when use Embedded Capacitance Material
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Bruce <bruce@xxxxxxxxxx>
- Date: Sat, 11 May 2013 03:45:03 -0700
Bruce, if the discrete PDN to PCB power cavity resonance occurs well
above the PCB to IC package cut-off, then the internal power of the IC
will not be substantially affected by the discrete PDN to PCB power
cavity resonance.
The biggest improvement from thin dielectrics is reduction in L. That is
what lets us get rid of discrete capacitors on the PCB. For Farads per
dollar it's hard to beat an MLCC capacitor. All the Farads in the world
don't help if the charge can't get to the load because of loop inductance.
Steve.
On 5/11/2013 3:15 AM, Bruce wrote:
> Hi Steve
>
> Good suggestion.
> Actually. It's not so easy to get enough information from IC vendor.
>
> In my case, the anti-resonance point is higher than 100M. And I read the
> book from Eric. Could I ignore the high frequency peak?
> In other projects with Intel and Qualcomm Chipset. I just only care about
> the PDN impedance below 100M( Sometimes is below 20M)
>
> If so. My confuse is the reason to choose Embedded Capacitance Material. ECM
> are more works well in higher frequency.
>
> I read all the answer carefully. But maybe Power integrity is much more
> controversial topic.
> I know a whole simulation from Chip to Chip is always a good choice. But the
> model is also always a problem.
>
> So in my case. Maybe evaluating in the lab is the final solution. Am I
> right?
>
> Best Regards,
> Bruce Wu
>
> Bruce determining acceptable impedance vs frequency for a PDN is the first
> and most important design step. While it is often difficult to get
> information from IC suppliers there is no good substitute for this
> step no matter what is needed to take care of it:
>
> * Very conservative design, What is conservative enough?
> |--- Plan on evaluating in the lab and hope you have enough flexibility
> to make any needed adjustments.
> * Measurement of key ICs in advance
> * Beat on the IC suppliers until they supply needed data
>
> Steve.
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of Bruce
> Sent: Friday, May 10, 2013 6:56 PM
> To: 'Istvan Novak'
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: anti-resonance point when use Embedded Capacitance
> Material
>
> Hi Istvan
>
> Thanks for your answer. My concern is how I can determine whether the
> resonance causes a problem for power, signal integrity and EMI?
> There are some solution come to my mind
> 1. Base on operate frequency of ICs. I believe this is not enough.
> 2. If I can get the CPM model. I can simulate the current and get the
> answer, But CPM file is not so easy to get it.
> 3. SSN simulation. But it also a little big challenge to run an accurate
> SSN simulation because of Model problem
> 4. Base on test. But that is after test. We need judge it before prototype
> Any other good method to determine the resonance is a problem or not? Thanks
>
>
> Best Regards,
> Bruce Wu
>
> -----Original Message-----
> From: Istvan Novak [mailto:istvan.novak@xxxxxxxxxxx]
> Sent: Thursday, May 09, 2013 8:17 PM
> To: bruce@xxxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] anti-resonance point when use Embedded Capacitance
> Material
>
> Hi Bruce,
>
> The anti-resonance between the static capacitance of planes and
> inductance of bypass capacitors will always be present unless you either
> match the plane impedance with the ESRs of capacitors or overwhelm the
> antiresonance with MANY low-inductance bypass capacitors. The
> antiresonance is present with any laminate material, thin or thick.
> When you use thin laminates (Embedded Capacitance Material), the
> resonance magnitude and frequency both get lower with respect to a
> thicker laminate. First you have to determine whether the resonance
> causes a problem for power, signal integrity and EMI. If you dont
> excite the resonance, you dont need to care.
>
> Regards,
>
> Istvan Novak
> Oracle
>
>
>
>
> On 5/9/2013 2:26 AM, Bruce wrote:
>> Hi Expert
>>
>>
>> We use Embedded Capacitance Material for better PDN and less capacitor
>> component. According to PDN Simulation. We notice that is an
> anti-resonance
>> point between capacitor and Plane.
>>
>>
>>
>> We can find that when use Embedded Capacitance Material. There are much
>> better in most frequency but near anti-resonance point.
>>
>>
>>
>> In this case. We have to solution.
>>
>> 1. Try to reduce the anti-resonance point. We need many high frequency
>> capacitor component. That is not good because we want to reduce the number
>> of capacitor component. Our purpose is reduce 70% number of capacitor
>> component.
>>
>> 2. Keep this anti-resonance point. That maybe have a risk if there is
>> some noise by chance in this frequency
>>
>>
>>
>> How about your suggestion? Please let me know if my question is not clear
>> enough.
>>
>> Thanks
>>
>>
>>
>> Best Regards,
>>
>> Bruce Wu
>>
>>
>>
>>
>
>
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