[SI-LIST] Re: anti-resonance point when use Embedded Capacitance Material
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: Dennis Han <Dennis.Han@xxxxxxxxx>
- Date: Fri, 10 May 2013 17:34:47 -0400
Dennis
Ground planes on L2 and L(N-1) are sufficient.
You might want to look at those differential vias in three dimensions to
see if there might be any other direction that energy could leak. These
little details become significant at 28G rates.
regards,
Scott
On Fri, May 10, 2013 at 5:25 PM, Dennis Han <Dennis.Han@xxxxxxxxx> wrote:
> If there are ground planes just 3 to 4 mil below the top and above
> bottom layers, is the ground fill on the outside layers needed? I do use a
> 20 to 50 mil wide trace around the perimeter of the outside layers that
> have the ground vias.
>
>
>
> A good practice for differential vias is to use a GSSG set (4 vias) with
> defined spacing and anti-pad design for differential signals. Ground vias
> can be shared where space is tight.
>
>
>
>
>
>
>
> *From:* Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
> *Sent:* Friday, May 10, 2013 4:16 PM
> *To:* Dennis Han
> *Cc:* orphanou@xxxxxxxxxxxx; bradb@xxxxxxxxxxx; leeritchey@xxxxxxxxxxxxx;
> si-list@xxxxxxxxxxxxx
>
> *Subject:* Re: [SI-LIST] Re: anti-resonance point when use Embedded
> Capacitance Material
>
>
>
> 1) place a ground via where ever you can. After layout is complete. Pop
> ground vias in wherever possible.
>
>
>
> 2) top most plane layer should be ground
>
>
>
> 3) bottom most plane layer should be ground
>
>
>
> 4) be afraid of differential vias without nearby grounds.
>
>
>
>
>
>
>
> On Fri, May 10, 2013 at 3:24 PM, Dennis Han <Dennis.Han@xxxxxxxxx> wrote:
>
> I was going to suggest ground vias around the perimeter of the PCB, but I
> see youve already suggested that in another reply. Ive used that method
> for many years with the vias spaced about lambda/10. Any rules for its use
> that I may not have considered?
>
>
>
>
>
>
>
> *From:* Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
> *Sent:* Friday, May 10, 2013 1:59 PM
> *To:* orphanou@xxxxxxxxxxxx
> *Cc:* bradb@xxxxxxxxxxx; leeritchey@xxxxxxxxxxxxx; Dennis Han;
> si-list@xxxxxxxxxxxxx
> *Subject:* Re: [SI-LIST] Re: anti-resonance point when use Embedded
> Capacitance Material
>
>
>
> antonis
>
>
>
> Sure radiating edges are a problem. Ever seen a cable routed adjacent to
> the edge of a PCB in a chassis? Most radiation problems occur when
> external antennas (cable shields, metal patches, package metal lead frames
> and planes) couple resonances elsewhere.
>
>
>
> On Fri, May 10, 2013 at 2:39 PM, Antonis Orphanou <orphanou@xxxxxxxxxxxx>
> wrote:
>
> Is edge fringing a real concern here? The dielectric to air interface is
> highly reflective after all .....
> The first order radiation mechanism is image currents from resonating
> planes (and patch antenna concepts as earlier mentioned).
> An ideal capacitor array is like an EM wall that splits the power plane
> into smaller sections hence shifting the radiated spectrum and resonance
> frequencies higher up in spectrum. Can a realistic capacitor and its
> inductance achieve that task? Judging from earlier responses that sounds
> impossible....
>
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Bradley Brim
> Sent: Friday, May 10, 2013 11:16 AM
> To: leeritchey@xxxxxxxxxxxxx; dennis.han@xxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: anti-resonance point when use Embedded Capacitance
> Material
>
> Hi Lee,
> Plane pair cavity resonances contribute to emissions. The earliest power
> integrity experts seem to have been EMC engineers concerned less with PDN
> noise at devices and more concerned with reducing emissions from the PDN.
> One can even view the operation of a microstrip patch antenna as a form of
> plane pair resonance and its sole purpose is to send/receive radiated
> emissions.
>
> To address a topic of the original inquiry ...
> Smaller plane separation implies less area of equivalent magnetic current
> at the plane pair edge, or equivalently less local fringing field volume,
> and therefore lower emissions for a given field strength. However, the
> smaller the plane separation the higher the Q of the cavity can be,
> implying a higher field strength at the plane pair edges.
>
> At frequencies where the sum of mounting inductance and ESL for the cap do
> not combine to make them exceedingly high impedance they will certainly
> affect plane resonances, whether or not placed in a uniform or grid
> pattern. EMC engineers typically guide for a uniform/grid placement with
> spacing based on a fraction of the wavelength in the cavity material at the
> highest frequency of concern. I observe PI experts with access to
> simulation tools approach the issue by visualizing PDN cavity resonances
> and placing caps near voltage/impedance maxima. This may not eliminate all
> resonances and can serve to shift the resonances to other frequencies. An
> iterative process of analyzing and cap placement is pursued. I've seen
> cases where this can yield as many or more caps than a uniform/grid
> placement. A procedure to consider simultaneous placement of all required
> "emicaps" (rather than the iterative process that does not reexamine
> selection/placement from previous iterations) can yield
> significantly fewer caps for the same level of emissions.
>
> Best regards,
> -Brad
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Lee
> Sent: Friday, May 10, 2013 9:16 AM
> To: dennis.han@xxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: anti-resonance point when use Embedded Capacitance
> Material
>
> I have seen no evidence that plane resonances contribute to EMI or that
> distributing capacitors evenly over a plane has much effect on resonances.
> I do this so that there is an even distribution of "ground" vias across the
> planes as has been recommended by Istvan.
>
> -----Original Message-----
> From: Dennis
> Sent: Friday, May 10, 2013 7:09 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: anti-resonance point when use Embedded Capacitance
> Material
>
> There are also free spreadsheet calculators from Altera, Xilinx, and Terry
> Fox & Associates. KEMET Spice can be used for that purpose to some extent.
>
> Dennis
>
> --- In si-list@xxxxxxxxxxxxxxx, Ken Wyatt <ken@...> wrote:
> >
> > Thanks Chas,
> > I remember those days...things have progressed greatly.
> >
> > Do you, or the group, know of affordable simulation S/W (Ansoft, maybe?)
> > that would simulate plane resonances? My limited budget won't support
> > multi-G$ S/W, unfortunately. That would be pretty cool to be able to
> > simulate that. I saw a recent demo of HyperLynx that was impressive.
> >
> > I know Istvan has several Excel calculators that will model PDN
> > impedances.
> >
> > You coming to the Denver symposium this year?
> >
> > Cheers, Ken
> > ___________________
> > Kenneth Wyatt
> > Wyatt Technical Services LLC
> > Woodland Park, CO
> > ken@...
> > Web Newsletter
> > Connect with me on LinkedIn!
> >
> > On May 9, 2013, at 2:22 PM, Grasso, Charles wrote:
> >
> > > Hello Ken,
> > >
> > > When faced with large areas of pwb that have little or no components,
> it
> > > used common practice for EMI guys to add lossy caps (the lossier the
> > > better)
> > > to the planes in a regular pattern to minimize the effects of plane
> > > resonance. With modern simulation tools, the resonant modes of the
> > > planes
> > > can be simulated and caps added (in just the right spot!) to reduce the
> > > effect.
> > >
> > > Chas
> > >
> > > -----Original Message-----
> > > From: si-list-bounce@... [mailto:si-list-bounce@...] On Behalf Of
> Istvan
> > > Novak
> > > Sent: Thursday, May 09, 2013 7:23 AM
> > > To: Ken Wyatt
> > > Cc: bruce@...; si-list@...
> > > Subject: [SI-LIST] Re: anti-resonance point when use Embedded
> > > Capacitance Material
> > >
> > > Ken,
> > > Bypass capacitors with more lossy dielectrics do help somewhat, but the
> > > dielectric loss shows up strongly in the ESR only at frequencies much
> > > lower than the series resonance frequency, where we usually dont need
> > > the higher ESR. Very lossy (and sloppy) dielectrics, such as Z5U and
> > > Y5V are good for cheap consumer electronics, but for professional
> > > circuits there are many drawbacks and it is not the best thing to use
> > > them. Ceramic capacitors with user-defined ESR are available from two
> > > of the major capacitor vendors, so they can be used when we need the
> > > highest performance and can afford the higher cost for these parts.
> > >
> > > Regards,
> > >
> > > Istvan Novak
> > > Oracle
> > >
> > >
> > >
> > >
> > > On 5/9/2013 9:00 AM, Ken Wyatt wrote:
> > >> Hi Group & Bruce,
> > >>
> > >> I'm kind of a "newby" when it comes to SI, but am reading Lee Richey's
> > >> books on the subject.
> > >>
> > >> One thing he recommends for PDN designs is the use of bypass
> > >> capacitors with a more lossy dielectric (higher ESR), such as X5R, Z5U
> > >> or Y5V, to dampen the anti-resonance. Would this be a reasonable thing
> > >> to try?
> > >>
> > >> Ken
> > >> ___________________
> > >> Kenneth Wyatt
> > >> Wyatt Technical Services LLC
> > >> Woodland Park, CO
> > >> ken@... <mailto:ken@...> Web
> > >> <http://www.emc-seminars.com> Newsletter
> > >> <http://emc-seminars.us1.list-manage.com/subscribe?u7f203d1f64dd89f
> > >> 06b0c3f5&id 0f29a904> Connect with me on LinkedIn
> > >> <http://www.linkedin.com/in/kennethwyatt>!
> > >>
> > >> On May 9, 2013, at 5:16 AM, Istvan Novak wrote:
> > >>
> > >>> Hi Bruce,
> > >>>
> > >>> The anti-resonance between the static capacitance of planes and
> > >>> inductance of bypass capacitors will always be present unless you
> > >>> either match the plane impedance with the ESRs of capacitors or
> > >>> overwhelm the antiresonance with MANY low-inductance bypass
> > >>> capacitors. The antiresonance is present with any laminate material,
> > >>> thin or thick.
> > >>> When you use thin laminates (Embedded Capacitance Material), the
> > >>> resonance magnitude and frequency both get lower with respect to a
> > >>> thicker laminate. First you have to determine whether the resonance
> > >>> causes a problem for power, signal integrity and EMI. If you dont
> > >>> excite the resonance, you dont need to care.
> > >>>
> > >>> Regards,
> > >>>
> > >>> Istvan Novak
> > >>> Oracle
> > >>>
> > >>>
> > >>>
> > >>>
> > >>> On 5/9/2013 2:26 AM, Bruce wrote:
> > >>>> Hi Expert
> > >>>>
> > >>>>
> > >>>> We use Embedded Capacitance Material for better PDN and less
> > >>>> capacitor component. According to PDN Simulation. We notice that is
> > >>>> an anti-resonance point between capacitor and Plane.
> > >>>>
> > >>>>
> > >>>>
> > >>>> We can find that when use Embedded Capacitance Material. There are
> > >>>> much better in most frequency but near anti-resonance point.
> > >>>>
> > >>>>
> > >>>>
> > >>>> In this case. We have to solution.
> > >>>>
> > >>>> 1. Try to reduce the anti-resonance point. We need many high
> > >>>> frequency
> > >>>> capacitor component. That is not good because we want to reduce the
> > >>>> number of capacitor component. Our purpose is reduce 70% number of
> > >>>> capacitor component.
> > >>>>
> > >>>> 2. Keep this anti-resonance point. That maybe have a risk if
> > >>>> there is
> > >>>> some noise by chance in this frequency
> > >>>>
> > >>>>
> > >>>>
> > >>>> How about your suggestion? Please let me know if my question is not
> > >>>> clear enough.
> > >>>>
> > >>>> Thanks
> > >>>>
> > >>>>
> > >>>>
> > >>>> Best Regards,
> > >>>>
> > >>>> Bruce Wu
>
>
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> --
>
> Scott McMorrow
>
> Teraspeed Consulting Group LLC
>
> 16 Stormy Brook Road
>
> Falmouth, ME 04105
>
> (401) 284-1827 Business
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> http://www.teraspeed.com
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> Teraspeed® is the registered service mark of
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> --
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> Scott McMorrow
>
> Teraspeed Consulting Group LLC
>
> 16 Stormy Brook Road
>
> Falmouth, ME 04105
>
> (401) 284-1827 Business
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> http://www.teraspeed.com
>
> Teraspeed® is the registered service mark of
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