[SI-LIST] Re: anti-resonance point when use Embedded Capacitance Material

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Wed, 08 May 2013 23:40:30 -0700

Bruce, suppress the resonance with a matching zero.  If the tolerances 
are tight you can use two or more tightly spaced zeroes.

Steve.
On 5/8/2013 11:26 PM, Bruce wrote:
> Hi Expert
>   
>
> We use Embedded Capacitance Material for better PDN and less capacitor
> component. According to PDN Simulation. We notice that is an anti-resonance
> point between capacitor and Plane.
>
>   
>
> We can find that when use Embedded Capacitance Material. There are much
> better in most frequency but near anti-resonance point.
>
>   
>
> In this case. We have to solution.
>
> 1.     Try to reduce the anti-resonance point. We need many high frequency
> capacitor component. That is not good because we want to reduce the number
> of capacitor component. Our purpose is reduce 70% number of capacitor
> component.
>
> 2.     Keep this anti-resonance point. That maybe have a risk if there is
> some noise by chance  in this frequency
>
>   
>
> How about your suggestion? Please let me know if my question is not clear
> enough.
>
> Thanks
>
>   
>
> Best Regards,
>
> Bruce Wu
>
>   
>
>
>
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