[SI-LIST] Re: package SSN model accuracy requirements
- From: "Tracy Barclay" <Tracy.Barclay@xxxxxxxxxxxx>
- To: <yafei_bi@xxxxxxxxx>
- Date: Thu, 24 Mar 2005 13:20:23 -0800
Hi Yafei,
Saber is still around. The primary Saber markets are automotive and
aerospace.
http://www.synopsys.com/products/mixedsignal/saber/saber.html
Tracy Barclay
CAE
Synopsys
=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On
Behalf Of Yafei Bi
Sent: Thursday, March 24, 2005 09:11
To: gstokes@xxxxxxxxx; 'Chris.Cheng@xxxxxxxxxxxx'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: package SSN model accuracy requirements
Geoff,
Glad you brought up Saber & MSAT AMS-HDL.
I was a heavy Saber user for 2+ years and fortunate to
work at Analogy for a very short of time, and it was a
wonderful experience.
AMS is a powerfull tool, people(including me) have
used it for modeling devices(BJT, mosfet...), complex
systems(electrical, merchanical) and all kinds of
things. I am sure SSO can be properly modeled in AMS
also.
Having gone through the process of generating IBIS
models, if my customer ask for Verilog-AMS model of
the I/O, I will be more than happy to develop one. And
it will have the SSO properly modeled.
You see, if you ask for it, you will get it :-)...
Synopsys bought Avanti which had its own mixed signal
tool suit and looks like Saber is no longer marketed
alone any more.
Thanks
Yafei
--- Geoff Stokes <gstokes@xxxxxxxxx> wrote:
> I am surprised no-one in this thread has mentioned
> Saber (previously
> Analogy, now Synopsis) which has its own modelling
> language, not too
> difficult to learn, conforms to Kirchoff, and has a
> library of generalised
> models. Some years ago I implemented an
> experimental model for a GaAs
> MESFET in Saber. Significantly, Saber has not been
> heavily marketed in
> recent years - perhaps someone from Synopsis can
> tell us why?
>=20
> Cheers
> Geoff
>=20
> -----Original Message-----
> From: Chris Cheng [mailto:Chris.Cheng@xxxxxxxxxxxx]=20
> Sent: 24 March 2005 01:27
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: package SSN model accuracy
> requirements
>=20
> Arpad,
>=20
> I can give you an even simpler answer, ever since
> the existence of IBIS, it
> can't model a simple problem like SSO. If you are a
> customer, would you
> choose a method that may be error if it is done
> wrong but at least give you
> a chance to predict the problem if it is done right,
> or, something just
> can't do the analysis AT ALL ? There are many road
> accidents with cars, but
> that doesn't mean you have to walk to work.
>=20
> Let me repeat the question I've asked many many
> times, how many of the
> member of the Si-list who are NOT just professional
> standards attendee or
> EDA tool vendors and have real responsibility to
> design system are actually
> using a standard IBIS model to analyze SSO today ? I
> rest my case.
>=20
> Garbage in garbage out, no matter it is SPICE or
> IBIS. At the end, whoever
> give the model out has the ultimate responsibility.
> But ever since the
> existence of IBIS, it can't address the problem high
> performance design (SSO
> and receiver performance to name a few). You and I
> know that behavioral
> models can address those problems long time ago but
> look at how long since
> the first known successful attempt (if you disagree
> with me on that
> reference, ping me off-line) until the standard
> committee even catch up with
> the idea. Seven years is a very long time, people
> can earn sabbatical out of
> that. Am I supposed to wait for another sabbatical
> if I want to model my
> equalizing receivers ? I've got problems on things I
> need to ship tomorrow.=20
>=20
> Let's take a closer look at AMS
> Here are the claims :
>=20
> a) It abstract your I/O to protect your IP Well,
> Gary's reference seems to
> suggest every I/O design is as simple as a
> university paper so may be your
> company have no problem handing out the I/O state
> machine design. Is that
> true ?
> On the same reference we are led to believe a SPICE
> level=3D1'ish model is
> really a behavioral model, ok I dig it, but do you
> think your company
> lawyers and design managers will buy that and freely
> handing it out without
> encryption ?
>=20
> Like I said before, it's like asking "Can you tell
> me the secret of your
> company ?"
> Ans : "I can't tell you in English, but I can tell
> you in Martians (just not
> to offend my earthly friends :-D)"=20
> Is that really possible (besides the fact that there
> is no Martian)?
>=20
> b) It is accurate and fast
> I still haven't seen any mention of SSO or how AMS
> can handle power impact
> on the I/O, may be SSO is no longer an important
> issue for GB serial ports ?
> How does one handle such modulation by predriver and
> substrate feedback from
> multiple power sources (core power for predriver,
> I/O power for main driver)
> without resorting to those level=3D1'ish transistor
> model ? A marketing paper
> like what Gary present can carefully craft the
> example to the advantage of
> the simulator but in reality how many interconnect
> is one simple S-parameter
> deck ? I would bet the real customer topology will
> more like a mix bag of
> circuit elements different vendor provide such as
> chip package, transmission
> line, terminators, discrets, connector models. How
> the speed of AMS will do
> when it is overloaded with a lot more circuit
> elements like R,L,C,
> transmission lines and S-parameters by different
> components ?
> Let's focus more on this little problem like a
> receiver, if you have to use
> the output of the receiver to predict a equalization
> how would you use your
> behavioral models to predict that ? Just take a look
> at those typical crazy
> FSB ringback, over-drive specs. Try a few case of
> real over drive and ring
> back cases which depends on common, differential
> mode, operating point, over
> drive, hysteretic etc and try construct a
> multi-dimensional equation/table
> to describe it and let's see how fast you will get.
> Ask the friends we both
> know and have already make pitches in this thread
> what do they think ? I am
> a fair person, show me a real life case and data and
> I will be convinced.
>=20
> c) It is standard and everyone support it I still
> couldn't figure out
> whether AMS is VHDL-AMS or Verilog-AMS, which one we
> are talk about here ?
> Can you tell me ?
> Does everyone use the same encryption to protect
> your IP ? If every tool has
> a different encryption, what kind of ZBB do you
> think you will get for ten
> different kinds of encryptors from ten different
> vendors ?
>=20
>=20
>=20
> -----Original Message-----
> From: Muranyi, Arpad
> [mailto:arpad.muranyi@xxxxxxxxx]
> Sent: Wednesday, March 23, 2005 11:54 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: package SSN model accuracy
> requirements
>=20
>=20
> Chris,
>=20
> The same is also true for SPICE! You are putting
> your faith into those
> engineer's hands who write your process files. And
> the average circuit
> designer usually has no clue for how to correct a
> bad transistor process
> file. Many times they don't even know where the
> limitations of the model
> are that they are using...
>=20
> Having worked for the same company I work for, you
> should remember some of
> the horror stories from those good old days when the
> IV curve of certain
> transistor models were on the order of 2-3x away
> from measurements... And
> what did we do to get a quick fix? We tweaked the
> .OPTIONS and did tricks
> with other simulation parameters because the process
> files were not going to
> change any time soon. (Good luck doing this
> independently for the N and P
> transistors). But I think I may have already said
> too much, so I will stop
> right here.
>=20
> Arpad
>
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>
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> =3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D
>=20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] =3D
> On Behalf Of Chris Cheng
> Sent: Wednesday, March 16, 2005 3:31 PM
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: package SSN model accuracy
> requirements
>=20
=3D=3D=3D message truncated =3D=3D=3D
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