[SI-LIST] Re: package SSN model accuracy requirements
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 9 Mar 2005 11:24:59 -0800
Ray,
That's a good point.
Once again, I am a true n00b on FPGA's so please tell me how a typical SSO
analysis a vendor provide to the customer then ?
Is is an IBIS package model combine with SPICE model of the driver receiver
?
Or is it just a set of IBIS package with IBIS I/O model and some "best
wishes, I think it will work" ?
I keep hearing in the recent threads about SSO noise in FPGA packages but I
have yet to hear customers of FPGA came out and say "we've done the SSO
analysis, this package will work" or "we've done the SSO analysis, this
package will not work and we avoided a disater".
Can someone share with me how exactly a customer of FPGA is expected to do
SSO analysis ?
If you tell me you don't since "I've done it for ten years and it worked so
it will work in the future". That's fine with me too.
But it will not be fair to say, "my vendor screw me and I have a noisy SSO
package" but yet you have done nothing to simulate the noise ahead of time.
I have to admit I am an ASIC kinda guy with my own I/O and package design.
Lately I am feeling the heat to look into more generic solutions like FPGA
so I am personally curious about how people really do it.
-----Original Message-----
From: Ray Anderson [mailto:ray.anderson@xxxxxxxxxx]
Sent: Wednesday, March 09, 2005 8:48 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: package SSN model accuracy requirements
Chris-
I think you may be misinterpreting what Lynne and the other posters in
this thread have been discussing so far.
No one seems to be saying that SSO simulations should be done with IBIS
(as it stands today).
The discussion is centered around the various package models. An IBIS
model consists of the silicon model portion and the package model
portion. One can take the package model portion (that is described in
IBIS syntax) and rewrite it in Spice syntax if you so desire. So while
some of the statements earlier in the thread may have referenced "IBIS
lumped models" and "IBIS ICM" models, the crux of the discussion is
related to model topologies, model complexity, model bandwidth, and
model size where the "model" in question is the package model. All of
these model attributes are relevant to SSO simulations regardless of
what you choose as the silicon driver model.
-Ray
Chris Cheng wrote:
>You can say what you want with IBIS, at the end of the day (today, not
>tomorrow or some future spec), can you do an SSO analysis based on a pure
>IBIS model ?
>
>I am a complete N00b on FPGA so I am curious how many people really do SSO
>analysis with just a standard IBIS description of a chip. I can't, so
please
>tell me how you did it.
>
>Those who know me and my previous life somewhere should remember some of
>those reference SPICE SSO models I generated, there is only a small number
>of SPICE drivers, interconnect and receivers set that need to be included
to
>accurately model SSO, x-talk, package/interconnect loss. Remember, m=x is a
>very powerful macro that doesn't even need to be an integer.
>
>Another interesting side note, some of the so call speedy "IBIS engines"
end
>up barely faster or even slower in some cases when the same interconnect
>complexity is added to get the accuracy close to acceptable level.
>
>All of the above SSO modelling methodolgies are well documented and
>correlated with actual characterization numbers. I am not talking about
>vaporware analysis here.
>
>
--
Raymond Anderson
Senior Signal Integrity Staff Engineer
Product Technology Dept.
Package Engineering Group
Xilinx Inc.
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