[SI-LIST] Re: package SSN model accuracy requirements
- From: steve weir <weirsi@xxxxxxxxxx>
- To: hassan@xxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Sat, 12 Mar 2005 14:07:28 -0800
Hassan, have a look at the current IBIS Summit presentations. Here, we can
see example differences between the current 4.1 standard and SPICE models
that have led to the BIRD95 and BIRD97 proposals. I for one would say
those example differences are quite substantial. BIRD95 adds the
substantial contribution of the predriver current ( which is shown to
actually exceed the PU current for some cases assuming it is powered from
Vddq ), but does not account for voltage variations caused by other outputs
coupled through the same interconnect. BIRD97 deals with that, by feeding
the Vddq voltage back into the predriver transfer function. IBIS3.2
doesn't do any of this.
So, how faithful can IBIS3.2 be to any large parallel bus even at
comparatively low speeds when it does not faithfully represent the I/O
driver current in the presence of SSO? And I think that there we can find
at least a qualitative answer to your question rephrased as "What are the
boundaries to which IBIS3.2 is useful?" These two BIRDs effectively
state: "Only to the point that either predriver current and dynamic Vddq
do not substantively alter the transfer function." ( And not to miss
Chris' points: this presumes the topology that BIRD95, and BIRD97 address. )
Regards,
Steve.
At 03:48 PM 3/12/2005 -0600, Hassan O. Ali wrote:
>Ray Anderson wrote:
>
> >Chris seems to favor Hspice models for doing SSN simulations (certainly
> >an option), Gary is a proponent of Eldo, AMS and n-port package models
> >does anyone else have opinions on what other solutions for SSN
> >simulations (or what works for them) are out there that can be utilized
> >today (are IBIS 3.2 models "good enough" for SSN today??) ?
> >
> >
>This thread has certainly been very interesting and informative. It
>would be even more interesting if the arguments were supported with
>quantitave/qualitative data.
>
>We've been told that IBIS 3.2 models cannot be relied upon to perform
>SSN analysis, but we've not yet been told how do IBIS 3.2 models compare
>in accuracy/speed against the more favored (transistor level) HSPICE
>models in today's designs.
>
>It would benefit us a lot if the arguments were specific enough to say,
>for example, IBIS 3.2 models are not good for which types of I/O
>technologies, I/O interfaces, data/clock speeds, signal rise/fall times,
>chip package technologies, PCB implementations, etc. And if IBIS 3.2
>models are not good, we've to be told, in a quantifiable manner, how bad
>they are.
>
>With my limited knowledge, I always thought I could use the HSPICE
>simulator to perfrom SSN analysis with IBIS 3.2 models. I always thought
>I could use the following combination of models to successfully perform
>SSN analysis using the HSPICE simulator:
>
>- IBIS 3.2 models of I/O buffers of all the devices involved (not
>including device packages)
>- S-parameter package models of all the devices involved with I/O and
>near-by power/ground pins as extracted using such tools as Ansoft HFSS.
>(Note here: this could be a partitioned package model)
>- HSPICE netlist with the PCB trace models (in W-element format) as
>extracted using such tools as Allegro PCB SI
>
>Again, with my limited knowledge, I always thought that SSN is largely a
>function of signal edge rates, and as long as IBIS models could
>faithfully provide those, I was OK, especially with the tremendous
>simulation speed enhancement of IBIS models.
>
>Please someone tell me if my thoughts are wrong.
>
>Best regards.
>
>Hassan.
>
>
>
>
>
>
>
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