[SI-LIST] Re: package SSN model accuracy requirements
- From: Heyfitch <heyfitch@xxxxxxxx>
- To: billw@xxxxxxxxxxx, SI List <si-list@xxxxxxxxxxxxx>
- Date: Tue, 8 Mar 2005 11:33:33 -0800 (PST)
Bill, thank you for sharing your thoughts on this issue. The first two points
you made lend themselves more readily to modeling of an ASIC package rather
than an FPGA one. In ASICs, you indeed assign signals in a self-repeating
pattern that has translational symmetry in X and Y directions, at least within
a single interface.
Frankly, I expected that many more SI-list participants would speak up on this
issue. It's easy to talk about this with wide brush strokes. But, apparently,
it's not that simple to formulate a set of specific requirements for the SSN
package simulation model you'd like to see from your IC vendor. With opening
this thread, I am inviting all of you - those who have already given it a lot
of thought and those who are just now beginning to delve into these issues - to
voice there wishes and concerns. This is an opportunity to be heard by all IC
vendors, who certainly will take cues from this thread. On a very basic level,
this thread may be an opportunity for system designers to voice their
"SSN-Simulation-wish-list" for their IC vendors.
The lack of response to my original posting may indicate that: either 1) this
is an issue of scarce interest and significance, or 2) I failed to frame well,
or 3) everyone is gone fishing ... to the PCB-West, and next week we should see
a flood of replies to this thread.
Regards.
-Vadim
Altera Corp.
Disclaimer: statements and opinions expressed here are my own and not those of
my employer.
----------------------------------------------------------------------------------------------------------------------------------
Bill Wurst <billw@xxxxxxxxxxx> wrote:
Vadim,
1) From my own experience, usually packages are somewhat symmetrical in
layout, i.e., they are divided up into identical or very similar sections.
Use the symmetry to advantage to keep the model as small as possible.
2) It is entirely possible to achieve very accurate simulations of a 64 bit
bus by simulating only a byte (or some other portion) based on the symmetry
of the package.
3) As Albert Einstein once said, "Everything should be kept as simple as
possible, but no simpler." Given that, I don't know that it's possible to
predict simulation time, as it greatly depends on the specifics of your
situation. However, simulations of a PDS are sometimes best run in batch
mode overnight.
Hope this helps.
-Bill
William C. Wurst William C. Wurst 3 5 2004-09-03T11:07:00Z
2004-10-28T23:52:00Z 1 30 176 Advanced Electronic Concepts, LLC 1 1 205
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-Bill ========================== Heyfitch wrote: I would like to hear
opinions of system SI engineers on the following subject. If your silicon
vendor provided you with a simulation model of an IC package - be it ASIC or
FPGA - intended to simulate SSN (caused by the IC package), what would your
requirements to that model be ? More specifically: 1) How many signal pins
should such a model include: 10, 20, ...100? The answer to this question
would probably be driven by the interface width. Correct? 2) What kind of
accuracy would you deem useful at all? How would you define "accuracy" in
this context? 3) As one should expect, package model accuracy comes at the
expense of model complexity. The complex model would take more CPU time to
run than a simpler one. What would be the acceptable trade-off between the
accuracy, the simulation speed, and the size of the package model (a.k.a.
number of IO pins)? What would be the acceptable simulation time (if defined
for 100ns transient run)?? I appreciate your feedback. -Vadim Heyfitch
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