[SI-LIST] package SSN model accuracy requirements
- From: Heyfitch <heyfitch@xxxxxxxx>
- To: SI List <si-list@xxxxxxxxxxxxx>
- Date: Mon, 7 Mar 2005 14:34:22 -0800 (PST)
I would like to hear opinions of system SI engineers on the following subject.
If your silicon vendor provided you with a simulation model of an IC package -
be it ASIC or FPGA - intended to simulate SSN (caused by the IC package), what
would your requirements to that model be ? More specifically:
1) How many signal pins should such a model include: 10, 20, ...100? The answer
to this question would probably be driven by the interface width. Correct?
2) What kind of accuracy would you deem useful at all? How would you define
"accuracy" in this context?
3) As one should expect, package model accuracy comes at the expense of model
complexity. The complex model would take more CPU time to run than a simpler
one. What would be the acceptable trade-off between the accuracy, the
simulation speed, and the size of the package model (a.k.a. number of IO pins)?
What would be the acceptable simulation time (if defined for 100ns transient
run)??
I appreciate your feedback.
-Vadim Heyfitch
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