[SI-LIST] Re: package SSN model accuracy requirements
- From: steve weir <weirsi@xxxxxxxxxx>
- To: heyfitch@xxxxxxxx, billw@xxxxxxxxxxx, SI List <si-list@xxxxxxxxxxxxx>
- Date: Tue, 08 Mar 2005 13:18:29 -0800
Vadim,
I agree with Bill's sentiment of "just enough". This places some burden on
the IC vendors as they would then need to evaluate results to see that they
are providing "enough" information. How much is enough? Enough to me is
what will get us to within 10% noise level and 10% of the actual timing
changes that we will really see under live conditions versus a simple IBIS
model driving against nominal driver / package parasitic capacitance at
both ends and a stock 50 ohm Tx line. ( Although, given modern boards, I
think 43 ohms s/b what we move the packages towards. )
The basic idea is that a chip vendor would begin with a very complete (
sic massive model ) as the golden reference and then exercise simplified
models of increasing complexity until the simplified results correlate
adequately in simulation and with test vehicles. At that point, the
simplified model would be the one provided to customers.
Here are some suggestions:
Core power distribution
Enough of the package / IC PDN to be able to match the board design to the
device power requirements.
I don't think this will require more than the parameters of the first LPF
pole pair, because beyond that pair, there is likely very little that can
be done on the board to control care and feeding of the beast.
What we really lack though is an impedance versus frequency requirement
that ties to application code.
There may be special circumstances that are peculiar to a given die or die
/ package combination that require additional data. For example analog
Vcc's that power PLLs or SERDES elements can be quite sensitive to
transverse digital noise currents. I would really like to know the
sensitivity as a PSRR frequency plot, and again the first order model of
any in-package distribution / bypass network(s). This will make it easier
to determine the need for board level decoupling networks and their
performance requirements.
I/O Signal integrity
A multi-line model that includes both enough lines and enough of the return
path detail so that noise may be determined within 10-20% of actual levels,
and signal timing aberrations may also be determined to an accuracy of
10-20%. If the package has super returns this might only require a few
lines. If the package is a wire bond, it will likely require many. For
the time being, I think we are stuck with coupled multi-stage R-L-C SPICE
models.
Regards,
Steve.
At 11:33 AM 3/8/2005 -0800, Heyfitch wrote:
>Bill, thank you for sharing your thoughts on this issue. The first two
>points you made lend themselves more readily to modeling of an ASIC
>package rather than an FPGA one. In ASICs, you indeed assign signals in a
>self-repeating pattern that has translational symmetry in X and Y
>directions, at least within a single interface.
>
>Frankly, I expected that many more SI-list participants would speak up on
>this issue. It's easy to talk about this with wide brush strokes. But,
>apparently, it's not that simple to formulate a set of specific
>requirements for the SSN package simulation model you'd like to see from
>your IC vendor. With opening this thread, I am inviting all of you -
>those who have already given it a lot of thought and those who are just
>now beginning to delve into these issues - to voice there wishes and
>concerns. This is an opportunity to be heard by all IC vendors, who
>certainly will take cues from this thread. On a very basic level, this
>thread may be an opportunity for system designers to voice their
>"SSN-Simulation-wish-list" for their IC vendors.
>
>The lack of response to my original posting may indicate that: either 1)
>this is an issue of scarce interest and significance, or 2) I failed to
>frame well, or 3) everyone is gone fishing ... to the PCB-West, and next
>week we should see a flood of replies to this thread.
>
>Regards.
>-Vadim
>Altera Corp.
>
>Disclaimer: statements and opinions expressed here are my own and not
>those of my employer.
>----------------------------------------------------------------------------------------------------------------------------------
>Bill Wurst <billw@xxxxxxxxxxx> wrote:
>
>Vadim,
>
>1) From my own experience, usually packages are somewhat symmetrical in
>layout, i.e., they are divided up into identical or very similar sections.
>Use the symmetry to advantage to keep the model as small as possible.
>
>2) It is entirely possible to achieve very accurate simulations of a 64 bit
>bus by simulating only a byte (or some other portion) based on the symmetry
>of the package.
>
>3) As Albert Einstein once said, "Everything should be kept as simple as
>possible, but no simpler." Given that, I don't know that it's possible to
>predict simulation time, as it greatly depends on the specifics of your
>situation. However, simulations of a PDS are sometimes best run in batch
>mode overnight.
>
>Hope this helps.
>
>-Bill
>
>William C. Wurst William C. Wurst 3 5 2004-09-03T11:07:00Z
>2004-10-28T23:52:00Z 1 30 176 Advanced Electronic Concepts, LLC 1 1 205
>11.6360 200 Clean Clean false false false M icrosoftInternetExplorer4 /*
>Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal";
>mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes;
>mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt;
>mso-para-margin:0in; mso-para-margin-bottom:.0001pt;
>mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New
>Roman";mso-ansi-language:#0400; mso-fareast-language:#0400;
>mso-bidi-language:#0400;}
>
>-Bill ========================== Heyfitch wrote: I would like to hear
>opinions of system SI engineers on the following subject. If your silicon
>vendor provided you with a simulation model of an IC package - be it ASIC or
>FPGA - intended to simulate SSN (caused by the IC package), what would your
>requirements to that model be ? More specifically: 1) How many signal pins
>should such a model include: 10, 20, ...100? The answer to this question
>would probably be driven by the interface width. Correct? 2) What kind of
>accuracy would you deem useful at all? How would you define "accuracy" in
>this context? 3) As one should expect, package model accuracy comes at the
>expense of model complexity. The complex model would take more CPU time to
>run than a simpler one. What would be the acceptable trade-off between the
>accuracy, the simulation speed, and the size of the package model (a.k.a.
>number of IO pins)? What would be the acceptable simulation time (if defined
>for 100ns transient run)?? I appreciate your feedback. -Vadim Heyfitch
>------------------------------------------------------------------ To
>unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx[1] with
>'unsubscribe'in the Subject field or to administer your membership from a
>webpage, go to: //www.freelists.org/webpage/si-list[2] For help:
>si-list-request@xxxxxxxxxxxxx[3] with 'help' in the Subject field List FAQ
>wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ[4] List
>technical documents are available at: http://www.si-list.org[5] List
>archivesare viewable at: //www.freelists.org/archives/si-list[6] or at
>our remote archives: http://groups.yahoo.com/group/si-list/messages[7] Old
>(prior to June 6, 2001) list archives are viewable at:
>http://www.qsl.net/wb6tpu[8]
>
>--- Links ---
>1 mailto:si-list-request@xxxxxxxxxxxxx
>2 //www.freelists.org/webpage/si-list
>3 mailto:si-list-request@xxxxxxxxxxxxx
>4 http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>5 http://www.si-list.org
>6 //www.freelists.org/archives/si-list
>7 http://groups.yahoo.com/group/si-list/messages
>8 http://www.qsl.net/wb6tpu
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
>or to administer your membership from a web page, go to:
>//www.freelists.org/webpage/si-list
>
>For help:
>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>List FAQ wiki page is located at:
>http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>
>List technical documents are available at:
>http://www.si-list.org
>
>List archives are viewable at:
>//www.freelists.org/archives/si-list
>or at our remote archives:
>http://groups.yahoo.com/group/si-list/messages
>Old (prior to June 6, 2001) list archives are viewable at:
>http://www.qsl.net/wb6tpu
>
>
>
>
>
>
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
>or to administer your membership from a web page, go to:
>//www.freelists.org/webpage/si-list
>
>For help:
>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>List FAQ wiki page is located at:
> http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>
>List technical documents are available at:
> http://www.si-list.org
>
>List archives are viewable at:
> //www.freelists.org/archives/si-list
>or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
>Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
The weirsp@xxxxxxxxxx e-mail address will terminate March 31, 2005.
Please update your address book with weirsi@xxxxxxxxxx
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
