[minima] Re: KISS Mixer Musings
- From: Joshua Blanton <jtblanton@xxxxxxxxx>
- To: minima <minima@xxxxxxxxxxxxx>
- Date: Wed, 5 Mar 2014 22:58:59 -0500
Hi Joe,
Correct - I meant 0V between gate DC and source DC levels. I actually
achieved this by removing the voltage source from the top end of the bias
pot, so I had approximately 4.7k in parallel with 0.001uF from my sources
to ground (I'm writing from memory here, but I think that's right).
The gates didn't conduct because of one of two possibilities: 1, the
actual swing on each gate was insufficient (because of a lossy transformer
at the LO input), or 2, because the source voltage actually floated up. I
couldn't tell you which is correct - that's a question for next test time.
I do not know the 'on resistance' of my FETs, but the datasheet Idss value
is lower than a J310 so I will assume higher. My guess is that this value
is calculated from Idss and Vds - is that right? I've not seen that value
used with JFETs.
Finally, via was a stupid tablet auto complete mistake. I was trying to
say that my circuit allows the DC source voltage to float... I couldn't
begin to tell you what word I meant to write :-)
Thanks for the thoughts. It'll probably be several days before I have more
bench time, but I'll be happy to post more info (or run more requested
tests) when I do.
Josh, KB8NYP
Sent from my phone - please excuse my brevity.
On Mar 5, 2014 8:35 PM, "Joe Rocci" <joe@xxxxxxxxxx> wrote:
>
>
> Josh
> When yiu say you have no gate bias, do you mean 0 volts relative to the
> source? If so, then how do you avoid driving the gates into conduction?
> Also, do you know what the low-level dynamic channel resistance of your
> FETs are with zero volts gate bias? I think the J310 is about 30-50 ohms
> until the source-drain voltage gets to about a volt, then it becomes
> non-linear with increasing voltage until Idss is reached. At least that's
> what I see in the curves. Lower resistance would, of course, seem better.
>
> My suggestion about the xfmr turns was to lower the primary turns in order
> to get more secondary gate drive volts from your 8640.
>
> What is your "via" I'm not familiar with that term.
>
> Joe
> W3JDR
>
>
> Sent from my tablet
>
>
>
> -------- Original message --------
> From Joshua Blanton <jtblanton@xxxxxxxxx>
> Date: 03/05/2014 7:52 PM (GMT-05:00)
> To minima <minima@xxxxxxxxxxxxx>
> Subject [minima] Re: KISS Mixer Musings
>
>
> Hi Joe,
>
> I'm not actually using J310 FETs, as I have several hundred 2SK192A-BL
> parts that I choose to try.... The ones I used, with the pinch off that I
> matched, would be "best" suited with a LO peak to peak voltage of 2.4V
> (pinch off to almost forward conduction). My via is actually very similar
> to your self bias recommendation, but only because I need no bias 😀
>
> I am working on an LO amp to do some impedance matching (with a much
> higher output impedance, as I don't think that the mixer is actually
> consuming much power -it just needs a large voltage swing. I'll also look
> at transformer games, but the chores I'm using are pretty small and don't
> have much room for more bifilar windings...
>
> Thanks,
> Josh
>
> Sent from my phone - please excuse my brevity.
> On Mar 5, 2014 3:39 PM, "Joe Rocci" <joe@xxxxxxxxxx> wrote:
>
>> Josh
>>
>> My Spice modeling indicates that you need about 5Vpp of drive on the J310
>> gates in order to get best
>> insertion loss and IMD. The DC bias should be adjusted so that the positive
>> peaks of the LO on the gates
>>
>> are just below the point of gate conduction, or about +0.5Vpk referenced to
>> the source (around 2.0VDC bias)
>> .You should be able to get the excess insertion loss down to better than
>> -1.0dB relative to the 6dB theoretical
>>
>> case, meaning better than 7dB overall. Please try this if you re-run your
>> tests; you can possibly lower the turns
>> on your gate drive xfmr if your 8640 generator doesn't have enough "soup".
>> Also, please see my previous post
>>
>> about modifying the circuit so that it automatically biases itself for the
>> amount of LO available.
>>
>> Joe
>> W3JDR
>>
>> -----------------------------------------------
>>
>> Mark and group,
>>
>> So I re-ran some tests, and I can answer (I think!) a number of questions
>> that I had about my first set of data. First of all, my bias issues are
>> entirely due to my drive levels being low, since I used a 50-ohm signal
>> generator for the LO port and my input transformer is lossy. The SI570
>> output of the Minima should generate much higher voltage swings (with much
>> lower LO power altogether!), which is an ideal drive for these parts. At
>> some point I'll switch to a square-wave drive and possibly a better input
>> transformer, and I think I'll need bias. So ... we can leave that question
>> aside for now; in the Minima, it should behave reasonably as long as your
>> FETs don't have a large pinchoff voltage. My best-case conversion loss was
>> 7.45dB, when I was driving into the mixer with +22.49dBm of LO power
>> (again, a 50ohm generator sine wave - not at all ideal for this circuit!
>> At this level, I probably should have used some gate bias, but I didn't -
>> too many moving parts and too little test time...); this is the maximum
>> power I can get out of my generator setup, and the 8640 angrily flashes its
>> "reduce output power" light :-) With +10dBm LO input, my conversion loss
>> is 9.32dB, which is not horrible.
>>
>> My 1dB compression point for this mixer, when driven at +10dBm LO power, is
>> around +1.5dBm (no compression is seen until the input power reaches
>> -6dBm). Again, this seems like a nice mixer for its parts count and
>> simplicity.
>>
>> As far as the harmonics and unwanted products go, I ran a test with 14MHz
>> RF (-10dBm) and 34MHz LO (+10dBm); the conversion loss in this case was
>> 11.6dB, as my transformers aren't super-hot down "that low" (this is an LO
>> input limitation, as both the 20MHz and 48MHz outputs are the same power).
>> Given the conversion loss, my IF output was -21.6dBm; the most powerful
>> unwanted output was at 28MHz, where there was a -49dBm spur (-26.4dB from
>> the wanted IF output). After that, there was a 40MHz spur at -55.7dBm
>> (-34.1dB from the wanted IF output), LO leakage at -57dBm (-35.4dB from the
>> wanted IF output), an RF->IF leakage at -58dBm (-36.4dB from the wanted IF
>> output), and that's pretty much it under 50MHz.
>>
>> Overall, the unwanted signals aren't too ugly. I at some point will re-run
>> the chain in the reverse direction; if it's symmetric, and 2*IF->RF is the
>> only real spur of note "nearby", then there might not be a strong need for
>> extra bandpass output filtering on TX - because 2*IF is already above
>> 30MHz, so the normal LPF will knock it down. The LO leakage might be the
>> biggest concern, when the LO is near a filter edge...
>>
>> Anyway, more data. Sorry if this is beyond the scope of the list - I might
>> actually build a Minima at some point, but mostly I was very intrigued by
>> the building blocks! I've been wanting to build a JFET mixer for years,
>> and this was the first design that I ran across that motivated me enough to
>> build it.
>>
>> Josh, KB8NYP
>>
>>
>>
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