Since the FETs are being used as switches we want the operation to be in the ohmic region. For a given Vds a higher Idss means that the slope of the drain characteristic is steeper in the ohmic region or in other words the on resistance rdson is lower which is beneficial in reducing loss through the switch.
On 28/02/2014 11:30 PM, pakdeDar wrote:
How about other spec required for this kind of mixer Joe ? I learn much from this discussion that high JFET Idss was specified as J310, BW10 but not MPF102 or other General FET .. Just a question from unexperienced builder..hihi.. Sudarmanta - YC1DCN Send from my TelakaspaBerrylayauw ® -----Original Message----- From: Joe Street<jstreet@xxxxxxxxxxxx> Sender: minima-bounce@xxxxxxxxxxxxx Date: Fri, 28 Feb 2014 23:20:37 To:<minima@xxxxxxxxxxxxx> Reply-To: minima@xxxxxxxxxxxxx Subject: [minima] Re: KISS Mixer Musings SST/U401 VGSth matched to within 5mv On 28/02/2014 11:13 PM, Joe Street wrote:Why not look for a monolithic pair? If they are fabricated on the same substrate the characteristics should be well matched. I haven't looked but surely there must be something off the shelf? On 28/02/2014 7:54 PM, Tayloe, Dan (NSN - US/Tempe) wrote:We need to bias the jfet channel for 50% on, 50% off. When a jfet is "on", it grounds its winding with its phasing for RF to IF transfer. Alternating jfets flips the signal to the opposite polarity. Rapidly flipping the signal polarity through this stage at the LO rate does the mixing. Thus there is no DC current, but we are trying to turn on/off AC paths. Since jfet pinch off thresholds vary so much from device to device, separate bias is best. As a matter of fact, if you had a bunch of these, it would be nice to match Idss and pinchoff voltage for these two jfets. - Dan Sent from my Windows Phone -----Original Message----- From: ext Joe Street Sent: 2/28/2014 5:10 PM To: minima@xxxxxxxxxxxxx Subject: [minima] Re: KISS Mixer Musings These FETs are not really 'biased' in the normal sense anyways because the drains are open circuit for DC so there is no bias current flowing. What you are doing is raising and lowering the potential of the whole channel. Variation in the device fabrication processes result in device to device variance in transconductance so perhaps in this strange circuit balance is more important?? On 28/02/2014 4:58 PM, Tayloe, Dan (NSN - US/Tempe) wrote:That might change the balance of the mixer, but does not change the bias on each gate. - Dan -----Original Message----- From: minima-bounce@xxxxxxxxxxxxx [mailto:minima-bounce@xxxxxxxxxxxxx] On Behalf Of ext Sandeep Lohia Sent: Friday, February 28, 2014 2:56 PM To: minima@xxxxxxxxxxxxx Subject: [minima] Re: KISS Mixer Musings http://4.bp.blogspot.com/-fIABMtTpyUE/Ut9yfPotc0I/AAAAAAAAAUQ/IG6TveVonrw/s1600/under+R&D.jpg NOTE : not yet tested live...IF you have two separate bias pots, You could bias the two JFETs with separate pots and adjust for similar drain Just thinking about this. I remember that the transconductance of JFETS varies quite a bit so the fact that the signals are not symetrical might be due to an imbalance in the device characteristics?Please take a look at the link and then any volunteers who can try and explain this to me most welcome!