[SI-LIST] Re: termination for routing 8 SDRAMs to single Processor
- From: "Ho, Koon Gee" <koon-gee-hkg.ho@xxxxxx>
- To: <aavinda12@xxxxxxxxx>, <for_si_list@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 15 Aug 2005 10:53:24 +0800
Hi Alex,
I'm just curious which simulating tools are you using. Is it Pspice or
something else?
Thanks,
Trish
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Aravnda G
Sent: Saturday, August 13, 2005 7:49 AM
To: for_si_list@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: termination for routing 8 SDRAMs to single
Processor
Hi All,
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I have been simulating various topologies for the data lines and found
the following to be working well (within dc, ac spec, good noise margin
levels, etc.):
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a balanced T with 45Ohm series termination at the beginning of the T
junction.=20
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Does this seem correct or are there any possible issues with this
topology?
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I tried shunt termination at the controller side but this really reduced
the noise margin to below 50mV though it is otherwise meeting the spec.
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Regards,
Alex.
> Hi All,
> I am working with a micro-processor conneted to 8 SDRAM with 12
address lines to all SDRAMs and 32 data lines each to two sets of four
SDRAMs. I was wondering if anyone has managed to route this sort of
topology without using terminations. If so please send information on
topology used. The IO are lvttl compatible at 3.3V. Any input on routing
possibilities is welcome.
>=20
> Thanks & Regards,
> Alex.
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